Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 316a88da authored by Alexander Stein's avatar Alexander Stein Committed by Nicolas Ferre
Browse files

ARM: at91/dt: at91sam9x5: Add CAN device nodes



Add the missing CAN devices node including their pin muxing to the shared
.dtsi for at91sam9x5. Actually include this file.

Signed-off-by: default avatarAlexander Stein <alexander.stein@systec-electronic.com>
Acked-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 5563d348
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@
#include "at91sam9x5_usart3.dtsi"
#include "at91sam9x5_macb0.dtsi"
#include "at91sam9x5_macb1.dtsi"
#include "at91sam9x5_can.dtsi"

/ {
	model = "Atmel AT91SAM9X25 SoC";
+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@

#include "at91sam9x5.dtsi"
#include "at91sam9x5_macb0.dtsi"
#include "at91sam9x5_can.dtsi"

/ {
	model = "Atmel AT91SAM9X35 SoC";
+40 −0
Original line number Diff line number Diff line
@@ -26,6 +26,46 @@
					};
				};
			};

			can0: can@f8000000 {
				compatible = "atmel,at91sam9x5-can";
				reg = <0xf8000000 0x300>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_can0_rx_tx>;
				clocks = <&can0_clk>;
				clock-names = "can_clk";
				status = "disabled";
			};

			can1: can@f8004000 {
				compatible = "atmel,at91sam9x5-can";
				reg = <0xf8004000 0x300>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_can1_rx_tx>;
				clocks = <&can1_clk>;
				clock-names = "can_clk";
				status = "disabled";
			};

			pinctrl@fffff400 {
				can0 {
					pinctrl_can0_rx_tx: can0_rx_tx {
						atmel,pins =
							<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0, conflicts with DRXD */
							AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX0, conflicts with DTXD */
					};
				};

				can1 {
					pinctrl_can1_rx_tx: can1_rx_tx {
						atmel,pins =
							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1, conflicts with RXD1 */
							AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX1, conflicts with TXD1 */
					};
				};
			};
		};
	};
};