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Commit 3164888a authored by Marta Lofstedt's avatar Marta Lofstedt Committed by Imre Deak
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drm/i915: Increase poll time for BDW FCLK_DONE 

During IGT testing it has been shown that the specification
defined polling time of 1 us for FCLK_DONE, is sometimes not
enough. The issue is still reproducible while disabling
C-states through the PM QoS framework and also while disabling
preemtion. From this the most plausible explanation is that the
issue is due to a firmware flaw.
As a workaround, it is better to wait a little bit longer for
the FCLK_DONE to come around, than to leave with an DRM_ERROR
and having FCLK_DONE at a randome time after.
While spinning a list of igt tests prone to reproduce the issue
the FCLK_DONE poll failed at approximately 2% of the invocations
of the bdw_set_cdclk function. The longest poll time during this
testing was measured to ~7us. So, the suggested new poll time of
100us is on the safe side.

v2: Added more documentation about investigations done.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102243


Signed-off-by: default avatarMarta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908132829.6312-1-marta.lofstedt@intel.com
parent d0d5e0d7

drivers/gpu/drm/i915/intel_cdclk.c

+5 −1
Original line number Diff line number Diff line
@@ -669,8 +669,12 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
	val |= LCPLL_CD_SOURCE_FCLK;

	I915_WRITE(LCPLL_CTL, val);



	/*

	 * According to the spec, it should be enough to poll for this 1 us.

	 * However, extensive testing shows that this can take longer.

	 */

	if (wait_for_us(I915_READ(LCPLL_CTL) &

			LCPLL_CD_SOURCE_FCLK_DONE, 1))

			LCPLL_CD_SOURCE_FCLK_DONE, 100))

		DRM_ERROR("Switching to FCLK failed\n");



	val = I915_READ(LCPLL_CTL);