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Commit 30d88c0e authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
Browse files

arm64: entry: Apply BP hardening for suspicious interrupts from EL0 



It is possible to take an IRQ from EL0 following a branch to a kernel
address in such a way that the IRQ is prioritised over the instruction
abort. Whilst an attacker would need to get the stars to align here,
it might be sufficient with enough calibration so perform BP hardening
in the rare case that we see a kernel address in the ELR when handling
an IRQ from EL0.

Reported-by: default avatarDan Hettena <dhettena@nvidia.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 5dfc6ed2

arch/arm64/kernel/entry.S

+5 −0
Original line number Diff line number Diff line
@@ -828,6 +828,11 @@ el0_irq_naked: 
#endif



	ct_user_exit

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

	tbz	x22, #55, 1f

	bl	do_el0_irq_bp_hardening

1:

#endif

	irq_handler



#ifdef CONFIG_TRACE_IRQFLAGS

arch/arm64/mm/fault.c

+6 −0
Original line number Diff line number Diff line
@@ -708,6 +708,12 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, 
	arm64_notify_die("", regs, &info, esr);

}



asmlinkage void __exception do_el0_irq_bp_hardening(void)

{

	/* PC has already been checked in entry.S */

	arm64_apply_bp_hardening();

}



asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr,

						   unsigned int esr,

						   struct pt_regs *regs)