Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 307d9008 authored by Mihai Caraman's avatar Mihai Caraman Committed by Alexander Graf
Browse files

KVM: PPC: e500: Add support for TLBnPS registers 



Add support for TLBnPS registers available in MMU Architecture Version
(MAV) 2.0.

Signed-off-by: default avatarMihai Caraman <mihai.caraman@freescale.com>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 8893a188

Documentation/virtual/kvm/api.txt

+4 −0
Original line number Diff line number Diff line
@@ -1803,6 +1803,10 @@ registers, find a list below: 
  PPC   | KVM_REG_PPC_TLB1CFG	| 32

  PPC   | KVM_REG_PPC_TLB2CFG	| 32

  PPC   | KVM_REG_PPC_TLB3CFG	| 32

  PPC   | KVM_REG_PPC_TLB0PS	| 32

  PPC   | KVM_REG_PPC_TLB1PS	| 32

  PPC   | KVM_REG_PPC_TLB2PS	| 32

  PPC   | KVM_REG_PPC_TLB3PS	| 32



ARM registers are mapped using the lower 32 bits.  The upper 16 of that

is the register group type, or coprocessor number:

arch/powerpc/include/asm/kvm_host.h

+1 −0
Original line number Diff line number Diff line
@@ -502,6 +502,7 @@ struct kvm_vcpu_arch { 
	spinlock_t wdt_lock;

	struct timer_list wdt_timer;

	u32 tlbcfg[4];

	u32 tlbps[4];

	u32 mmucfg;

	u32 epr;

	u32 crit_save;

arch/powerpc/include/uapi/asm/kvm.h

+4 −0
Original line number Diff line number Diff line
@@ -465,5 +465,9 @@ struct kvm_get_htab_header { 
#define KVM_REG_PPC_TLB1CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)

#define KVM_REG_PPC_TLB2CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)

#define KVM_REG_PPC_TLB3CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)

#define KVM_REG_PPC_TLB0PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)

#define KVM_REG_PPC_TLB1PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)

#define KVM_REG_PPC_TLB2PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)

#define KVM_REG_PPC_TLB3PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)



#endif /* __LINUX_KVM_POWERPC_H */

arch/powerpc/kvm/e500.h

+18 −0
Original line number Diff line number Diff line
@@ -23,6 +23,10 @@ 
#include <asm/mmu-book3e.h>

#include <asm/tlb.h>



enum vcpu_ftr {

	VCPU_FTR_MMU_V2

};



#define E500_PID_NUM   3

#define E500_TLB_NUM   2
@@ -299,4 +303,18 @@ static inline unsigned int get_tlbmiss_tid(struct kvm_vcpu *vcpu) 
#define get_tlb_sts(gtlbe)              (MAS1_TS)

#endif /* !BOOKE_HV */



static inline bool has_feature(const struct kvm_vcpu *vcpu,

			       enum vcpu_ftr ftr)

{

	bool has_ftr;

	switch (ftr) {

	case VCPU_FTR_MMU_V2:

		has_ftr = ((vcpu->arch.mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2);

		break;

	default:

		return false;

	}

	return has_ftr;

}



#endif /* KVM_E500_H */

arch/powerpc/kvm/e500_emulate.c

+10 −0
Original line number Diff line number Diff line
@@ -284,6 +284,16 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val) 
	case SPRN_TLB1CFG:

		*spr_val = vcpu->arch.tlbcfg[1];

		break;

	case SPRN_TLB0PS:

		if (!has_feature(vcpu, VCPU_FTR_MMU_V2))

			return EMULATE_FAIL;

		*spr_val = vcpu->arch.tlbps[0];

		break;

	case SPRN_TLB1PS:

		if (!has_feature(vcpu, VCPU_FTR_MMU_V2))

			return EMULATE_FAIL;

		*spr_val = vcpu->arch.tlbps[1];

		break;

	case SPRN_L1CSR0:

		*spr_val = vcpu_e500->l1csr0;

		break;