Merge "ARM: dts: msm: Add ufs crypto engine node for lagoon"

		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};

	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

			<&gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&gcc GCC_UFS_PHY_AHB_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_UFS_CFG 0 0>,    /* No vote */

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_UFS_CFG 1000 0>;

				 /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};

	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;

		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;

		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */