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Commit 2f7989ef authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: 6226/1: fix kprobe bug in ldr instruction emulation
  ARM: Update mach-types
  ARM: lockdep: fix unannotated irqs-on
  ARM: 6184/2: ux500: use neutral PRCMU base
  ARM: 6212/1: atomic ops: add memory constraints to inline asm
  ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unless
  ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
parents 6f7dd68b 0ebe25f9

arch/arm/include/asm/atomic.h

+66 −66
Original line number Diff line number Diff line
@@ -40,12 +40,12 @@ static inline void atomic_add(int i, atomic_t *v) 
	int result;



	__asm__ __volatile__("@ atomic_add\n"

"1:	ldrex	%0, [%2]\n"

"	add	%0, %0, %3\n"

"	strex	%1, %0, [%2]\n"

"1:	ldrex	%0, [%3]\n"

"	add	%0, %0, %4\n"

"	strex	%1, %0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "Ir" (i)

	: "cc");

}
@@ -58,12 +58,12 @@ static inline int atomic_add_return(int i, atomic_t *v) 
	smp_mb();



	__asm__ __volatile__("@ atomic_add_return\n"

"1:	ldrex	%0, [%2]\n"

"	add	%0, %0, %3\n"

"	strex	%1, %0, [%2]\n"

"1:	ldrex	%0, [%3]\n"

"	add	%0, %0, %4\n"

"	strex	%1, %0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "Ir" (i)

	: "cc");
@@ -78,12 +78,12 @@ static inline void atomic_sub(int i, atomic_t *v) 
	int result;



	__asm__ __volatile__("@ atomic_sub\n"

"1:	ldrex	%0, [%2]\n"

"	sub	%0, %0, %3\n"

"	strex	%1, %0, [%2]\n"

"1:	ldrex	%0, [%3]\n"

"	sub	%0, %0, %4\n"

"	strex	%1, %0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "Ir" (i)

	: "cc");

}
@@ -96,12 +96,12 @@ static inline int atomic_sub_return(int i, atomic_t *v) 
	smp_mb();



	__asm__ __volatile__("@ atomic_sub_return\n"

"1:	ldrex	%0, [%2]\n"

"	sub	%0, %0, %3\n"

"	strex	%1, %0, [%2]\n"

"1:	ldrex	%0, [%3]\n"

"	sub	%0, %0, %4\n"

"	strex	%1, %0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "Ir" (i)

	: "cc");
@@ -118,11 +118,11 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) 


	do {

		__asm__ __volatile__("@ atomic_cmpxchg\n"

		"ldrex	%1, [%2]\n"

		"ldrex	%1, [%3]\n"

		"mov	%0, #0\n"

		"teq	%1, %3\n"

		"strexeq %0, %4, [%2]\n"

		    : "=&r" (res), "=&r" (oldval)

		"teq	%1, %4\n"

		"strexeq %0, %5, [%3]\n"

		    : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)

		    : "r" (&ptr->counter), "Ir" (old), "r" (new)

		    : "cc");

	} while (res);
@@ -137,12 +137,12 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) 
	unsigned long tmp, tmp2;



	__asm__ __volatile__("@ atomic_clear_mask\n"

"1:	ldrex	%0, [%2]\n"

"	bic	%0, %0, %3\n"

"	strex	%1, %0, [%2]\n"

"1:	ldrex	%0, [%3]\n"

"	bic	%0, %0, %4\n"

"	strex	%1, %0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (tmp), "=&r" (tmp2)

	: "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)

	: "r" (addr), "Ir" (mask)

	: "cc");

}
@@ -249,7 +249,7 @@ static inline u64 atomic64_read(atomic64_t *v) 
	__asm__ __volatile__("@ atomic64_read\n"

"	ldrexd	%0, %H0, [%1]"

	: "=&r" (result)

	: "r" (&v->counter)

	: "r" (&v->counter), "Qo" (v->counter)

	);



	return result;
@@ -260,11 +260,11 @@ static inline void atomic64_set(atomic64_t *v, u64 i) 
	u64 tmp;



	__asm__ __volatile__("@ atomic64_set\n"

"1:	ldrexd	%0, %H0, [%1]\n"

"	strexd	%0, %2, %H2, [%1]\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"	strexd	%0, %3, %H3, [%2]\n"

"	teq	%0, #0\n"

"	bne	1b"

	: "=&r" (tmp)

	: "=&r" (tmp), "=Qo" (v->counter)

	: "r" (&v->counter), "r" (i)

	: "cc");

}
@@ -275,13 +275,13 @@ static inline void atomic64_add(u64 i, atomic64_t *v) 
	unsigned long tmp;



	__asm__ __volatile__("@ atomic64_add\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"	adds	%0, %0, %3\n"

"	adc	%H0, %H0, %H3\n"

"	strexd	%1, %0, %H0, [%2]\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	adds	%0, %0, %4\n"

"	adc	%H0, %H0, %H4\n"

"	strexd	%1, %0, %H0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "r" (i)

	: "cc");

}
@@ -294,13 +294,13 @@ static inline u64 atomic64_add_return(u64 i, atomic64_t *v) 
	smp_mb();



	__asm__ __volatile__("@ atomic64_add_return\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"	adds	%0, %0, %3\n"

"	adc	%H0, %H0, %H3\n"

"	strexd	%1, %0, %H0, [%2]\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	adds	%0, %0, %4\n"

"	adc	%H0, %H0, %H4\n"

"	strexd	%1, %0, %H0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "r" (i)

	: "cc");
@@ -315,13 +315,13 @@ static inline void atomic64_sub(u64 i, atomic64_t *v) 
	unsigned long tmp;



	__asm__ __volatile__("@ atomic64_sub\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"	subs	%0, %0, %3\n"

"	sbc	%H0, %H0, %H3\n"

"	strexd	%1, %0, %H0, [%2]\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	subs	%0, %0, %4\n"

"	sbc	%H0, %H0, %H4\n"

"	strexd	%1, %0, %H0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "r" (i)

	: "cc");

}
@@ -334,13 +334,13 @@ static inline u64 atomic64_sub_return(u64 i, atomic64_t *v) 
	smp_mb();



	__asm__ __volatile__("@ atomic64_sub_return\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"	subs	%0, %0, %3\n"

"	sbc	%H0, %H0, %H3\n"

"	strexd	%1, %0, %H0, [%2]\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	subs	%0, %0, %4\n"

"	sbc	%H0, %H0, %H4\n"

"	strexd	%1, %0, %H0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "r" (i)

	: "cc");
@@ -358,12 +358,12 @@ static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new) 


	do {

		__asm__ __volatile__("@ atomic64_cmpxchg\n"

		"ldrexd		%1, %H1, [%2]\n"

		"ldrexd		%1, %H1, [%3]\n"

		"mov		%0, #0\n"

		"teq		%1, %3\n"

		"teqeq		%H1, %H3\n"

		"strexdeq	%0, %4, %H4, [%2]"

		: "=&r" (res), "=&r" (oldval)

		"teq		%1, %4\n"

		"teqeq		%H1, %H4\n"

		"strexdeq	%0, %5, %H5, [%3]"

		: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)

		: "r" (&ptr->counter), "r" (old), "r" (new)

		: "cc");

	} while (res);
@@ -381,11 +381,11 @@ static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new) 
	smp_mb();



	__asm__ __volatile__("@ atomic64_xchg\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"	strexd	%1, %3, %H3, [%2]\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	strexd	%1, %4, %H4, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)

	: "r" (&ptr->counter), "r" (new)

	: "cc");
@@ -402,16 +402,16 @@ static inline u64 atomic64_dec_if_positive(atomic64_t *v) 
	smp_mb();



	__asm__ __volatile__("@ atomic64_dec_if_positive\n"

"1:	ldrexd	%0, %H0, [%2]\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	subs	%0, %0, #1\n"

"	sbc	%H0, %H0, #0\n"

"	teq	%H0, #0\n"

"	bmi	2f\n"

"	strexd	%1, %0, %H0, [%2]\n"

"	strexd	%1, %0, %H0, [%3]\n"

"	teq	%1, #0\n"

"	bne	1b\n"

"2:"

	: "=&r" (result), "=&r" (tmp)

	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter)

	: "cc");
@@ -429,18 +429,18 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u) 
	smp_mb();



	__asm__ __volatile__("@ atomic64_add_unless\n"

"1:	ldrexd	%0, %H0, [%3]\n"

"	teq	%0, %4\n"

"	teqeq	%H0, %H4\n"

"1:	ldrexd	%0, %H0, [%4]\n"

"	teq	%0, %5\n"

"	teqeq	%H0, %H5\n"

"	moveq	%1, #0\n"

"	beq	2f\n"

"	adds	%0, %0, %5\n"

"	adc	%H0, %H0, %H5\n"

"	strexd	%2, %0, %H0, [%3]\n"

"	adds	%0, %0, %6\n"

"	adc	%H0, %H0, %H6\n"

"	strexd	%2, %0, %H0, [%4]\n"

"	teq	%2, #0\n"

"	bne	1b\n"

"2:"

	: "=&r" (val), "=&r" (ret), "=&r" (tmp)

	: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)

	: "r" (&v->counter), "r" (u), "r" (a)

	: "cc");

arch/arm/kernel/entry-armv.S

+6 −10
Original line number Diff line number Diff line
@@ -162,8 +162,6 @@ ENDPROC(__und_invalid) 
	@  r4 - orig_r0 (see pt_regs definition in ptrace.h)

	@

	stmia	r5, {r0 - r4}



	asm_trace_hardirqs_off

	.endm



	.align	5
@@ -204,7 +202,7 @@ __dabt_svc: 
	@

	@ IRQs off again before pulling preserved data off the stack

	@

	disable_irq

	disable_irq_notrace



	@

	@ restore SPSR and restart the instruction
@@ -218,6 +216,9 @@ ENDPROC(__dabt_svc) 
__irq_svc:

	svc_entry



#ifdef CONFIG_TRACE_IRQFLAGS

	bl	trace_hardirqs_off

#endif

#ifdef CONFIG_PREEMPT

	get_thread_info tsk

	ldr	r8, [tsk, #TI_PREEMPT]		@ get preempt count
@@ -291,7 +292,7 @@ __und_svc: 
	@

	@ IRQs off again before pulling preserved data off the stack

	@

1:	disable_irq

1:	disable_irq_notrace



	@

	@ restore SPSR and restart the instruction
@@ -327,7 +328,7 @@ __pabt_svc: 
	@

	@ IRQs off again before pulling preserved data off the stack

	@

	disable_irq

	disable_irq_notrace



	@

	@ restore SPSR and restart the instruction
@@ -393,8 +394,6 @@ ENDPROC(__pabt_svc) 
	@ Clear FP to mark the first stack frame

	@

	zero_fp



	asm_trace_hardirqs_off

	.endm



	.macro	kuser_cmpxchg_check
@@ -465,9 +464,6 @@ __irq_usr: 
 THUMB(	movne	r0, #0		)

 THUMB(	strne	r0, [r0]	)

#endif

#ifdef CONFIG_TRACE_IRQFLAGS

	bl	trace_hardirqs_on

#endif



	mov	why, #0

	b	ret_to_user

arch/arm/kernel/kprobes-decode.c

+3 −2
Original line number Diff line number Diff line
@@ -583,13 +583,14 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs) 
{

	insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];

	kprobe_opcode_t insn = p->opcode;

	long ppc = (long)p->addr + 8;

	union reg_pair fnr;

	int rd = (insn >> 12) & 0xf;

	int rn = (insn >> 16) & 0xf;

	int rm = insn & 0xf;

	long rdv;

	long rnv  = regs->uregs[rn];

	long rmv  = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */

	long rnv = (rn == 15) ? ppc : regs->uregs[rn];

	long rmv = (rm == 15) ? ppc : regs->uregs[rm];

	long cpsr = regs->ARM_cpsr;



	fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);

arch/arm/kernel/process.c

+14 −9
Original line number Diff line number Diff line
@@ -351,17 +351,21 @@ EXPORT_SYMBOL(dump_fpu); 


/*

 * Shuffle the argument into the correct register before calling the

 * thread function.  r1 is the thread argument, r2 is the pointer to

 * the thread function, and r3 points to the exit function.

 * thread function.  r4 is the thread argument, r5 is the pointer to

 * the thread function, and r6 points to the exit function.

 */

extern void kernel_thread_helper(void);

asm(	".pushsection .text\n"

"	.align\n"

"	.type	kernel_thread_helper, #function\n"

"kernel_thread_helper:\n"

"	mov	r0, r1\n"

"	mov	lr, r3\n"

"	mov	pc, r2\n"

#ifdef CONFIG_TRACE_IRQFLAGS

"	bl	trace_hardirqs_on\n"

#endif

"	msr	cpsr_c, r7\n"

"	mov	r0, r4\n"

"	mov	lr, r6\n"

"	mov	pc, r5\n"

"	.size	kernel_thread_helper, . - kernel_thread_helper\n"

"	.popsection");
@@ -391,11 +395,12 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) 


	memset(&regs, 0, sizeof(regs));



	regs.ARM_r1 = (unsigned long)arg;

	regs.ARM_r2 = (unsigned long)fn;

	regs.ARM_r3 = (unsigned long)kernel_thread_exit;

	regs.ARM_r4 = (unsigned long)arg;

	regs.ARM_r5 = (unsigned long)fn;

	regs.ARM_r6 = (unsigned long)kernel_thread_exit;

	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;

	regs.ARM_pc = (unsigned long)kernel_thread_helper;

	regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;

	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;



	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);

}

arch/arm/mach-ux500/clock.c

+1 −1
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ EXPORT_SYMBOL(clk_disable); 
 */

static unsigned long clk_mtu_get_rate(struct clk *clk)

{

	void __iomem *addr = __io_address(U8500_PRCMU_BASE)

	void __iomem *addr = __io_address(UX500_PRCMU_BASE)

		+ PRCM_TCR;

	u32 tcr = readl(addr);

	int mtu = (int) clk->data;