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Commit 2f56f492 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Skip SP_INST_TAG and SP_INST_DATA dump in Snapshot for A615"

parents 844bdc28 01ec280b

drivers/gpu/msm/adreno_a6xx_snapshot.c

+65 −7
Original line number Diff line number Diff line
@@ -633,6 +633,49 @@ static struct a6xx_shader_block a6xx_shader_blocks[] = { 
	{A6XX_HLSQ_INDIRECT_META,         0x40,}

};



static struct a6xx_shader_block a615_shader_blocks[] = {

	{A6XX_TP0_TMO_DATA,               0x200},

	{A6XX_TP0_SMO_DATA,               0x80,},

	{A6XX_TP0_MIPMAP_BASE_DATA,       0x3C0},

	{A6XX_TP1_TMO_DATA,               0x200},

	{A6XX_TP1_SMO_DATA,               0x80,},

	{A6XX_TP1_MIPMAP_BASE_DATA,       0x3C0},

	{A6XX_SP_LB_0_DATA,               0x800},

	{A6XX_SP_LB_1_DATA,               0x800},

	{A6XX_SP_LB_2_DATA,               0x800},

	{A6XX_SP_LB_3_DATA,               0x800},

	{A6XX_SP_LB_4_DATA,               0x800},

	{A6XX_SP_LB_5_DATA,               0x200},

	{A6XX_SP_CB_BINDLESS_DATA,        0x800},

	{A6XX_SP_CB_LEGACY_DATA,          0x280,},

	{A6XX_SP_UAV_DATA,                0x80,},

	{A6XX_SP_CB_BINDLESS_TAG,         0x80,},

	{A6XX_SP_TMO_UMO_TAG,             0x80,},

	{A6XX_SP_SMO_TAG,                 0x80},

	{A6XX_SP_STATE_DATA,              0x3F},

	{A6XX_HLSQ_CHUNK_CVS_RAM,         0x1C0},

	{A6XX_HLSQ_CHUNK_CPS_RAM,         0x280},

	{A6XX_HLSQ_CHUNK_CVS_RAM_TAG,     0x40,},

	{A6XX_HLSQ_CHUNK_CPS_RAM_TAG,     0x40,},

	{A6XX_HLSQ_ICB_CVS_CB_BASE_TAG,   0x4,},

	{A6XX_HLSQ_ICB_CPS_CB_BASE_TAG,   0x4,},

	{A6XX_HLSQ_CVS_MISC_RAM,          0x1C0},

	{A6XX_HLSQ_CPS_MISC_RAM,          0x580},

	{A6XX_HLSQ_INST_RAM,              0x800},

	{A6XX_HLSQ_GFX_CVS_CONST_RAM,     0x800},

	{A6XX_HLSQ_GFX_CPS_CONST_RAM,     0x800},

	{A6XX_HLSQ_CVS_MISC_RAM_TAG,      0x8,},

	{A6XX_HLSQ_CPS_MISC_RAM_TAG,      0x4,},

	{A6XX_HLSQ_INST_RAM_TAG,          0x80,},

	{A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0xC,},

	{A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10},

	{A6XX_HLSQ_PWR_REST_RAM,          0x28},

	{A6XX_HLSQ_PWR_REST_TAG,          0x14},

	{A6XX_HLSQ_DATAPATH_META,         0x40,},

	{A6XX_HLSQ_FRONTEND_META,         0x40},

	{A6XX_HLSQ_INDIRECT_META,         0x40,}

};



static struct kgsl_memdesc a6xx_capturescript;

static struct kgsl_memdesc a6xx_crashdump_registers;

static bool crash_dump_valid;
@@ -2115,10 +2158,18 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev) 
	 * read the data) and then a block specific number of bytes to hold

	 * the data

	 */

	if (adreno_is_a615_family(adreno_dev)) {

		for (i = 0; i < ARRAY_SIZE(a615_shader_blocks); i++) {

			script_size += 32 * A6XX_NUM_SHADER_BANKS;

			data_size += a615_shader_blocks[i].sz *

				sizeof(unsigned int) * A6XX_NUM_SHADER_BANKS;

		}

	} else {

		for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++) {

			script_size += 32 * A6XX_NUM_SHADER_BANKS;

		data_size += a6xx_shader_blocks[i].sz * sizeof(unsigned int) *

			A6XX_NUM_SHADER_BANKS;

			data_size += a6xx_shader_blocks[i].sz *

				sizeof(unsigned int) * A6XX_NUM_SHADER_BANKS;

		}

	}



	/* Calculate the script and data size for MVC registers */
@@ -2224,8 +2275,15 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev) 
	}



	/* Program each shader block */

	for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++) {

		ptr += _a6xx_crashdump_init_shader(&a6xx_shader_blocks[i], ptr,

	if (adreno_is_a615_family(adreno_dev)) {

		for (i = 0; i < ARRAY_SIZE(a615_shader_blocks); i++)

			ptr += _a6xx_crashdump_init_shader(

					&a615_shader_blocks[i], ptr,

					&offset);

	} else {

		for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++)

			ptr += _a6xx_crashdump_init_shader(

					&a6xx_shader_blocks[i], ptr,

					&offset);

	}