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Commit 2ef9bdfe authored by Daniel Vetter's avatar Daniel Vetter Committed by Alex Deucher
Browse files

drm/radeon: add W|RREG32_IDX for MM_INDEX|DATA based mmio accesss 



Just refactoring to make the next patche simpler. Now all indirect register
access in the new modesetting driver should go through the r100_mm_(w|r)reg
fucntions.

RADEON_READ_MM from the old driver seems to be totally unused, so just kill
it.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9add1ac3

drivers/gpu/drm/radeon/r100.c

+6 −4
Original line number Diff line number Diff line
@@ -4135,9 +4135,10 @@ int r100_init(struct radeon_device *rdev) 
	return 0;

}



uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)

uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,

		      bool always_indirect)

{

	if (reg < rdev->rmmio_size)

	if (reg < rdev->rmmio_size && !always_indirect)

		return readl(((void __iomem *)rdev->rmmio) + reg);

	else {

		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -4145,9 +4146,10 @@ uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 
	}

}



void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,

		  bool always_indirect)

{

	if (reg < rdev->rmmio_size)

	if (reg < rdev->rmmio_size && !always_indirect)

		writel(v, ((void __iomem *)rdev->rmmio) + reg);

	else {

		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);

drivers/gpu/drm/radeon/radeon.h

+10 −6
Original line number Diff line number Diff line
@@ -1631,8 +1631,10 @@ int radeon_device_init(struct radeon_device *rdev, 
void radeon_device_fini(struct radeon_device *rdev);

int radeon_gpu_wait_for_idle(struct radeon_device *rdev);



uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);

void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,

		      bool always_indirect);

void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,

		  bool always_indirect);

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
@@ -1648,9 +1650,11 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 
#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))

#define RREG16(reg) readw((rdev->rmmio) + (reg))

#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))

#define RREG32(reg) r100_mm_rreg(rdev, (reg))

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))

#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))

#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))

#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)

#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
@@ -1675,7 +1679,7 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 
		tmp_ |= ((val) & ~(mask));			\

		WREG32_PLL(reg, tmp_);				\

	} while (0)

#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))

#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))

#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))

#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))

drivers/gpu/drm/radeon/radeon_combios.c

+2 −4
Original line number Diff line number Diff line
@@ -3246,11 +3246,9 @@ static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 
	while (ram--) {

		addr = ram * 1024 * 1024;

		/* write to each page */

		WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);

		WREG32(RADEON_MM_DATA, 0xdeadbeef);

		WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);

		/* read back and verify */

		WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);

		if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)

		if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)

			return 0;

	}

drivers/gpu/drm/radeon/radeon_cp.c

+0 −14
Original line number Diff line number Diff line
@@ -116,20 +116,6 @@ u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) 
	}

}



u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)

{

	u32 ret;



	if (addr < 0x10000)

		ret = DRM_READ32(dev_priv->mmio, addr);

	else {

		DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);

		ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);

	}



	return ret;

}



static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)

{

	u32 ret;

drivers/gpu/drm/radeon/radeon_cursor.c

+9 −8
Original line number Diff line number Diff line
@@ -66,24 +66,25 @@ static void radeon_hide_cursor(struct drm_crtc *crtc) 
	struct radeon_device *rdev = crtc->dev->dev_private;



	if (ASIC_IS_DCE4(rdev)) {

		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |

		WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,

			   EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |

			   EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));

	} else if (ASIC_IS_AVIVO(rdev)) {

		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));

		WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,

			   (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));

	} else {

		u32 reg;

		switch (radeon_crtc->crtc_id) {

		case 0:

			WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);

			reg = RADEON_CRTC_GEN_CNTL;

			break;

		case 1:

			WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);

			reg = RADEON_CRTC2_GEN_CNTL;

			break;

		default:

			return;

		}

		WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);

		WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);

	}

}