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Commit 2e9bebb4 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add initial PCIe2 pinctrl and devicetree node for kona"

parents 456bdace c972c646

arch/arm64/boot/dts/qcom/kona-pcie.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/clock/qcom,gcc-kona.h>



&soc {

	pcie2: qcom,pcie@1c10000 {

		compatible = "qcom,pci-msm";



		reg = <0x01c10000 0x4000>,

			<0x01c16000 0x2000>,

			<0x64000000 0xf1d>,

			<0x64000f20 0xa8>,

			<0x64001000 0x1000>,

			<0x64100000 0x100000>,

			<0x64200000 0x100000>,

			<0x64300000 0x4000000>;

		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",

				"io", "bars";



		cell-index = <2>;

		linux,pci-domain = <2>;



		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x01000000 0x0 0x64200000 0x64200000 0x0 0x100000>,

			<0x02000000 0x0 0x64300000 0x64300000 0x0 0x4000000>;



		interrupt-parent = <&pcie2>;

		interrupts = <0 1 2 3 4 5>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",

				"int_global_int";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH

				0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH

				0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH

				0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH

				0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH

				0 0 0 5 &pdc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;

		msi-parent = <&pcie2_msi>;



		perst-gpio = <&tlmm 85 0>;

		wake-gpio = <&tlmm 87 0>;

		pinctrl-names = "default";

		pinctrl-0 = <&pcie2_clkreq_default

				&pcie2_perst_default

				&pcie2_wake_default>;



		gdsc-vdd-supply = <&pcie_2_gdsc>;

		vreg-1p8-supply = <&pm8150_l9>;

		vreg-0p9-supply = <&pm8150_l5>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;

		qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>;

		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		qcom,msm-bus,name = "pcie2";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<108 512 0 0>,

				<108 512 500 800>;



		clocks = <&clock_gcc GCC_PCIE_2_PIPE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_PCIE_2_AUX_CLK>,

			<&clock_gcc GCC_PCIE_2_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_2_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_2_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_MDM_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE2_PHY_REFGEN_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;

		clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src",

				"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",

				"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",

				"pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_phy_aux_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;



		resets = <&clock_gcc GCC_PCIE_2_BCR>,

			<&clock_gcc GCC_PCIE_2_PHY_BCR>;

		reset-names = "pcie_2_core_reset",

				"pcie_2_phy_reset";



		qcom,smmu-sid-base = <0x1d00>;

		iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,

			<0x100 &apps_smmu 0x1d01 0x1>;



		qcom,boot-option = <0x1>;

		qcom,use-19p2mhz-aux-clk;

		qcom,no-l0s-supported;

		qcom,slv-addr-space-size = <0x4000000>;

		qcom,ep-latency = <10>;



		pcie2_rp: pcie2_rp {

			reg = <0 0 0 0 0>;

		};

	};



	pcie2_msi: qcom,pcie2_msi@17a00040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&intc>;

		interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;

	};

};

arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi

+41 −0
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@@ -147,5 +147,46 @@ 
				};

			};

		};



		pcie2 {

			pcie2_perst_default: pcie2_perst_default {

				mux {

					pins = "gpio85";

					function = "gpio";

				};



				config {

					pins = "gpio85";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			pcie2_clkreq_default: pcie2_clkreq_default {

				mux {

					pins = "gpio86";

					function = "pci_e1";

				};



				config {

					pins = "gpio86";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			pcie2_wake_default: pcie2_wake_default {

				mux {

					pins = "gpio87";

					function = "gpio";

				};



				config {

					pins = "gpio87";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};

	};

};

arch/arm64/boot/dts/qcom/kona-rumi.dtsi

+23 −0
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@@ -45,6 +45,29 @@ 
};



&soc {

	#address-cells = <1>;

	#size-cells = <1>;



	pcie2: qcom,pcie@1c10000 {

		reg = <0x01c10000 0x4000>,

			<0x01c16000 0x2000>,

			<0x64000000 0xf1d>,

			<0x64000f20 0xa8>,

			<0x64001000 0x1000>,

			<0x64100000 0x100000>,

			<0x64200000 0x100000>,

			<0x64300000 0x4000000>,

			<0x01c15000 0x1000>;

		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",

				"io", "bars", "rumi";



		qcom,target-link-speed = <0x1>;

		qcom,link-check-max-count = <200>; /* 1 sec */

		qcom,no-l1-supported;

		qcom,no-l1ss-supported;

		qcom,no-aux-clk-sync;

	};



	usb_emu_phy: usb_emu_phy@a720000 {

		compatible = "qcom,usb-emu-phy";

		reg = <0x0a720000 0x9500>,

arch/arm64/boot/dts/qcom/kona.dtsi

+2 −0
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@@ -30,6 +30,7 @@ 


	aliases {

		ufshc1 = &ufshc_mem; /* Embedded UFS slot */

		pci-domain2 = &pcie2; /* PCIe2 domain */

	};



	cpus {
@@ -1570,6 +1571,7 @@ 


#include "kona-bus.dtsi"

#include "kona-ion.dtsi"

#include "kona-pcie.dtsi"

#include "msm-arm-smmu-kona.dtsi"

#include "kona-pinctrl.dtsi"

#include "kona-smp2p.dtsi"