Merge "disp: msm: update DISP TCSR register in lito" (2e80fd0d) · Commits · e / devices / android_kernel_fairphone_FP4

msm/sde/sde_hw_catalog.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -4222,6 +4222,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->true_inline_prefill_fudge_lines = 2;
		sde_cfg->true_inline_prefill_lines_nv12 = 32;
		sde_cfg->true_inline_prefill_lines = 48;
		sde_cfg->update_tcsr_disp_glitch = true;
		} else if (IS_SDMTRINKET_TARGET(hw_rev)) {
		sde_cfg->has_cwb_support = true;
		sde_cfg->has_qsync = true;

+3 −0

Original line number	Diff line number	Diff line
		@@ -1273,6 +1273,8 @@ struct sde_limit_cfg {
		* @has_3d_merge_reset Supports 3D merge reset
		* @has_decimation Supports decimation
		* @has_qos_fl_nocalc flag to indicate QoS fill level needs no calculation
		* @update_tcsr_disp_glitch flag to enable HW workaround to avoid spurious
		* transactions during suspend
		* @sc_cfg: system cache configuration
		* @uidle_cfg Settings for uidle feature
		* @sui_misr_supported indicate if secure-ui-misr is supported
		@@ -1333,6 +1335,7 @@ struct sde_mdss_cfg {
		bool has_3d_merge_reset;
		bool has_decimation;
		bool has_qos_fl_nocalc;
		bool update_tcsr_disp_glitch;

		struct sde_sc_cfg sc_cfg;

+23 −0

Original line number	Diff line number	Diff line
		@@ -27,6 +27,7 @@
		#include <linux/dma-buf.h>
		#include <linux/memblock.h>
		#include <linux/bootmem.h>
		#include <soc/qcom/scm.h>

		#include "msm_drv.h"
		#include "msm_mmu.h"
		@@ -60,6 +61,8 @@
		#define MEM_PROTECT_SD_CTRL_SWITCH 0x18
		#define MDP_DEVICE_ID 0x1A

		#define TCSR_DISP_HF_SF_ARES_GLITCH_MASK 0x01FCA084

		static const char * const iommu_ports[] = {
		"mdp_0",
		};
		@@ -3368,6 +3371,23 @@ static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
		return rc;
		}

		static void _sde_kms_update_tcsr_glitch_mask(struct sde_kms *sde_kms)
		{
		u32 read_val, write_val;

		if (!sde_kms \|\| !sde_kms->catalog \|\|
		!sde_kms->catalog->update_tcsr_disp_glitch)
		return;

		read_val = scm_io_read(TCSR_DISP_HF_SF_ARES_GLITCH_MASK);
		write_val = read_val \| BIT(2);
		scm_io_write(TCSR_DISP_HF_SF_ARES_GLITCH_MASK, write_val);

		pr_info("tcsr glitch programmed read_val:%x write_val:%x\n",
		read_val, write_val);

		}

		static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
		struct drm_device *dev,
		struct msm_drm_private *priv)
		@@ -3394,6 +3414,9 @@ static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
		goto power_error;
		}

		/* mask glitch during gdsc power up */
		_sde_kms_update_tcsr_glitch_mask(sde_kms);

		/* initialize power domain if defined */
		rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
		if (rc) {