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Commit 2e13d643 authored by Laxminath Kasam's avatar Laxminath Kasam
Browse files

asoc: bolero: Update SWR TX moved to AO region 



In bengal target, SWR TX moved to AO region.
Update SWR TX as child of VA macro and handle
respective SWR register/clock sequences from
VA macro.

Change-Id: I6b632ce56a885f2ccc8516840b0e5d270fe0b2c0
Signed-off-by: default avatarLaxminath Kasam <lkasam@codeaurora.org>
parent 4651dcbb

asoc/bengal-port-config.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { 
};



static struct swr_mstr_port_map sm_port_map[] = {

	{TX_MACRO, SWR_UC0, tx_frame_params_default},

	{VA_MACRO, SWR_UC0, tx_frame_params_default},

	{RX_MACRO, SWR_UC0, rx_frame_params_default},

	{RX_MACRO, SWR_UC1, rx_frame_params_dsd},

};

asoc/codecs/bolero/bolero-cdc-registers.h

+1 −0
Original line number Diff line number Diff line
@@ -696,6 +696,7 @@ 
#define BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL	(VA_START_OFFSET + 0x0000)

#define BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \

						(VA_START_OFFSET + 0x0004)

#define BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL	(VA_START_OFFSET + 0x0008)

#define BOLERO_CDC_VA_TOP_CSR_TOP_CFG0		(VA_START_OFFSET + 0x0080)

#define BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL		(VA_START_OFFSET + 0x0084)

#define BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL		(VA_START_OFFSET + 0x0088)

asoc/codecs/bolero/bolero-cdc-regmap.c

+1 −0
Original line number Diff line number Diff line
@@ -609,6 +609,7 @@ static const struct reg_default bolero_defaults[] = { 
	/* VA macro */

	{ BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},

	{ BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},

	{ BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},

	{ BOLERO_CDC_VA_TOP_CSR_TOP_CFG0, 0x00},

	{ BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},

	{ BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},

asoc/codecs/bolero/bolero-cdc-tables.c

+2 −0
Original line number Diff line number Diff line
@@ -442,6 +442,7 @@ u8 bolero_rx_reg_access[BOLERO_CDC_RX_MACRO_MAX] = { 
u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = {

	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
@@ -567,6 +568,7 @@ u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = { 
u8 bolero_va_top_reg_access[BOLERO_CDC_VA_MACRO_TOP_MAX] = {

	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,

asoc/codecs/bolero/tx-macro.c

+29 −21
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ struct tx_macro_priv { 
	s32 dmic_6_7_clk_cnt;

	u16 dmic_clk_div;

	u32 version;

	u32 is_used_tx_swr_gpio;

	unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];

	unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];

	char __iomem *tx_io_base;
@@ -3046,6 +3047,7 @@ static int tx_macro_probe(struct platform_device *pdev) 
		sample_rate, tx_priv) == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED)

			return -EINVAL;

	}

	if (is_used_tx_swr_gpio) {

		tx_priv->reset_swr = true;

		INIT_WORK(&tx_priv->tx_macro_add_child_devices_work,

			  tx_macro_add_child_devices);
@@ -3056,9 +3058,10 @@ static int tx_macro_probe(struct platform_device *pdev) 
		tx_priv->swr_plat_data.clk = tx_macro_swrm_clock;

		tx_priv->swr_plat_data.core_vote = tx_macro_core_vote;

		tx_priv->swr_plat_data.handle_irq = NULL;



	mutex_init(&tx_priv->mclk_lock);

		mutex_init(&tx_priv->swr_clk_lock);

	}

	tx_priv->is_used_tx_swr_gpio = is_used_tx_swr_gpio;

	mutex_init(&tx_priv->mclk_lock);

	tx_macro_init_ops(&ops, tx_io_base);

	ops.clk_id_req = TX_CORE_CLK;

	ops.default_clk_id = TX_CORE_CLK;
@@ -3068,7 +3071,7 @@ static int tx_macro_probe(struct platform_device *pdev) 
			"%s: register macro failed\n", __func__);

		goto err_reg_macro;

	}



	if (is_used_tx_swr_gpio)

		schedule_work(&tx_priv->tx_macro_add_child_devices_work);

	pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);

	pm_runtime_use_autosuspend(&pdev->dev);
@@ -3079,6 +3082,7 @@ static int tx_macro_probe(struct platform_device *pdev) 
	return 0;

err_reg_macro:

	mutex_destroy(&tx_priv->mclk_lock);

	if (is_used_tx_swr_gpio)

		mutex_destroy(&tx_priv->swr_clk_lock);

	return ret;

}
@@ -3093,15 +3097,19 @@ static int tx_macro_remove(struct platform_device *pdev) 
	if (!tx_priv)

		return -EINVAL;



	if (tx_priv->is_used_tx_swr_gpio) {

		if (tx_priv->swr_ctrl_data)

			kfree(tx_priv->swr_ctrl_data);

		for (count = 0; count < tx_priv->child_count &&

			count < TX_MACRO_CHILD_DEVICES_MAX; count++)

		platform_device_unregister(tx_priv->pdev_child_devices[count]);

			platform_device_unregister(

				tx_priv->pdev_child_devices[count]);

	}



	pm_runtime_disable(&pdev->dev);

	pm_runtime_set_suspended(&pdev->dev);

	mutex_destroy(&tx_priv->mclk_lock);

	if (tx_priv->is_used_tx_swr_gpio)

		mutex_destroy(&tx_priv->swr_clk_lock);

	bolero_unregister_macro(&pdev->dev, TX_MACRO);

	return 0;