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Commit 2dfb765b authored by Rishabh Jain's avatar Rishabh Jain
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msm: camera: ope: Fix OPE clock issue 



Due to non-availability of all clock levels, while downgrading
or upgrading the clock rate, ope is voting for zero clock rate.
Fix issue by voting for nearest non-zero clockrate while
upgrading or downgrading the clock rate.

CRs-Fixed: 2649906
Change-Id: I2f3488084e0aa32ecfa84bcbebad887a1ef8409d
Signed-off-by: default avatarRishabh Jain <risjai@codeaurora.org>
parent 7ce0928a

drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c

+10 −4
Original line number Diff line number Diff line
@@ -1020,8 +1020,11 @@ static int cam_ope_get_lower_clk_rate(struct cam_ope_hw_mgr *hw_mgr, 


	i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk);



	if (i > 0)

	while (i > 0) {

		if (ctx_data->clk_info.clk_rate[i - 1])

			return ctx_data->clk_info.clk_rate[i - 1];

		i--;

	}



	CAM_DBG(CAM_OPE, "Already clk at lower level");
@@ -1035,8 +1038,11 @@ static int cam_ope_get_next_clk_rate(struct cam_ope_hw_mgr *hw_mgr, 


	i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk);



	if (i < CAM_MAX_VOTE - 1)

	while (i < CAM_MAX_VOTE - 1) {

		if (ctx_data->clk_info.clk_rate[i + 1])

			return ctx_data->clk_info.clk_rate[i + 1];

		i++;

	}



	CAM_DBG(CAM_OPE, "Already clk at higher level");