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Commit 2db97045 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Merge branch '4.2-fixes' into mips-for-linux-next

parents fb2646ab e0d8b2ec

arch/mips/include/asm/pgtable-bits.h

+9 −14
Original line number Diff line number Diff line
@@ -133,20 +133,13 @@ 
#define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)

#define _PAGE_SPLITTING_SHIFT	(_PAGE_HUGE_SHIFT + 1)

#define _PAGE_SPLITTING		(1 << _PAGE_SPLITTING_SHIFT)



/* Only R2 or newer cores have the XI bit */

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

#define _PAGE_NO_EXEC_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)

#else

#define _PAGE_GLOBAL_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)

#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)

#endif	/* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */



#endif	/* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */



#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

/* XI - page cannot be executed */

#ifndef _PAGE_NO_EXEC_SHIFT

#ifdef _PAGE_SPLITTING_SHIFT

#define _PAGE_NO_EXEC_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)

#else

#define _PAGE_NO_EXEC_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)

#endif

#define _PAGE_NO_EXEC		(cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
@@ -156,14 +149,16 @@ 
#define _PAGE_READ		(cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))

#define _PAGE_NO_READ_SHIFT	_PAGE_READ_SHIFT

#define _PAGE_NO_READ		(cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)

#endif	/* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */



#if defined(_PAGE_NO_READ_SHIFT)

#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)

#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)



#else	/* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */

#elif defined(_PAGE_SPLITTING_SHIFT)

#define _PAGE_GLOBAL_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)

#else

#define _PAGE_GLOBAL_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)

#endif

#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)

#endif	/* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */



#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)

#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)

arch/mips/include/uapi/asm/swab.h

+9 −3
Original line number Diff line number Diff line
@@ -16,11 +16,13 @@ 
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) ||		\

    defined(_MIPS_ARCH_LOONGSON3A)



static inline __attribute_const__ __u16 __arch_swab16(__u16 x)

static inline __attribute__((nomips16)) __attribute_const__

		__u16 __arch_swab16(__u16 x)

{

	__asm__(

	"	.set	push			\n"

	"	.set	arch=mips32r2		\n"

	"	.set	nomips16		\n"

	"	wsbh	%0, %1			\n"

	"	.set	pop			\n"

	: "=r" (x)
@@ -30,11 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x) 
}

#define __arch_swab16 __arch_swab16



static inline __attribute_const__ __u32 __arch_swab32(__u32 x)

static inline __attribute__((nomips16)) __attribute_const__

		__u32 __arch_swab32(__u32 x)

{

	__asm__(

	"	.set	push			\n"

	"	.set	arch=mips32r2		\n"

	"	.set	nomips16		\n"

	"	wsbh	%0, %1			\n"

	"	rotr	%0, %0, 16		\n"

	"	.set	pop			\n"
@@ -50,11 +54,13 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) 
 * 64-bit kernel on r2 CPUs.

 */

#ifdef __mips64

static inline __attribute_const__ __u64 __arch_swab64(__u64 x)

static inline __attribute__((nomips16)) __attribute_const__

		__u64 __arch_swab64(__u64 x)

{

	__asm__(

	"	.set	push			\n"

	"	.set	arch=mips64r2		\n"

	"	.set	nomips16		\n"

	"	dsbh	%0, %1			\n"

	"	dshd	%0, %0			\n"

	"	.set	pop			\n"

arch/mips/kernel/cps-vec.S

+2 −2
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ dcache_done: 


	/* Enter the coherent domain */

	li	t0, 0xff

	PTR_S	t0, GCR_CL_COHERENCE_OFS(v1)

	sw	t0, GCR_CL_COHERENCE_OFS(v1)

	ehb



	/* Jump to kseg0 */
@@ -302,7 +302,7 @@ LEAF(mips_cps_boot_vpes) 
	PTR_L	t0, 0(t0)



	/* Calculate a pointer to this cores struct core_boot_config */

	PTR_L	t0, GCR_CL_ID_OFS(t0)

	lw	t0, GCR_CL_ID_OFS(t0)

	li	t1, COREBOOTCFG_SIZE

	mul	t0, t0, t1

	PTR_LA	t1, mips_cps_core_bootcfg