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Commit 2d9bb18d authored by Neeraj Upadhyay's avatar Neeraj Upadhyay
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ARM: dts: msm: Enable bus scaling for CDSP PIL for Lito 

Add properties for enabling bus scaling for CDSP PIL on
Lito SoC.

Change-Id: I94e0681ac92ea4179fb3eeaef36f00f8bb308ae6
parent c6c37440

qcom/lito.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -1711,6 +1711,13 @@ 
		memory-region = <&pil_cdsp_mem>;

		qcom,complete-ramdump;



		qcom,msm-bus,name = "pil-cdsp";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<154 821 0 0>,

			<154 821 0 1>;



		/* Inputs from turing */

		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,

				<&cdsp_smp2p_in 0 0>,