Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2d61fe0f authored by Joe.C's avatar Joe.C Committed by James Liao
Browse files

clk: mediatek: add 13mhz clock for MT8173 



Add 13mhz clock used by GPT timer in infracfg.

Signed-off-by: default avatarYingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
parent 9ffecb10

drivers/clk/mediatek/clk-mt8173.c

+5 −0
Original line number Diff line number Diff line
@@ -619,6 +619,10 @@ static const struct mtk_gate infra_clks[] __initconst = { 
	GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),

};



static const struct mtk_fixed_factor infra_divs[] __initconst = {

	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),

};



static const struct mtk_gate_regs peri0_cg_regs = {

	.set_ofs = 0x0008,

	.clr_ofs = 0x0010,
@@ -754,6 +758,7 @@ static void __init mtk_infrasys_init(struct device_node *node) 


	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),

						clk_data);

	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

include/dt-bindings/clock/mt8173-clk.h

+2 −1
Original line number Diff line number Diff line
@@ -187,7 +187,8 @@ 
#define CLK_INFRA_CEC			9

#define CLK_INFRA_PMICSPI		10

#define CLK_INFRA_PMICWRAP		11

#define CLK_INFRA_NR_CLK		12

#define CLK_INFRA_CLK_13M		12

#define CLK_INFRA_NR_CLK		13



/* PERI_SYS */