Loading arch/blackfin/include/asm/io.h +51 −44 Original line number Diff line number Diff line Loading @@ -31,11 +31,13 @@ static inline unsigned char readb(const volatile void __iomem *addr) unsigned int val; int tmp; __asm__ __volatile__ ("cli %1;\n\t" "NOP; NOP; SSYNC;\n\t" "%0 = b [%2] (z);\n\t" "sti %1;\n\t" : "=d"(val), "=d"(tmp): "a"(addr) __asm__ __volatile__ ( "cli %1;" "NOP; NOP; SSYNC;" "%0 = b [%2] (z);" "sti %1;" : "=d"(val), "=d"(tmp) : "a"(addr) ); return (unsigned char) val; Loading @@ -46,11 +48,13 @@ static inline unsigned short readw(const volatile void __iomem *addr) unsigned int val; int tmp; __asm__ __volatile__ ("cli %1;\n\t" "NOP; NOP; SSYNC;\n\t" "%0 = w [%2] (z);\n\t" "sti %1;\n\t" : "=d"(val), "=d"(tmp): "a"(addr) __asm__ __volatile__ ( "cli %1;" "NOP; NOP; SSYNC;" "%0 = w [%2] (z);" "sti %1;" : "=d"(val), "=d"(tmp) : "a"(addr) ); return (unsigned short) val; Loading @@ -61,12 +65,15 @@ static inline unsigned int readl(const volatile void __iomem *addr) unsigned int val; int tmp; __asm__ __volatile__ ("cli %1;\n\t" "NOP; NOP; SSYNC;\n\t" "%0 = [%2];\n\t" "sti %1;\n\t" : "=d"(val), "=d"(tmp): "a"(addr) __asm__ __volatile__ ( "cli %1;" "NOP; NOP; SSYNC;" "%0 = [%2];" "sti %1;" : "=d"(val), "=d"(tmp) : "a"(addr) ); return val; } Loading Loading @@ -110,12 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define iowrite16_rep(a, s, c) writesw(a, s, c) #define iowrite32_rep(a, s, c) writesl(a, s, c) #define ioread8(X) readb(X) #define ioread16(X) readw(X) #define ioread32(X) readl(X) #define iowrite8(val,X) writeb(val,X) #define iowrite16(val,X) writew(val,X) #define iowrite32(val,X) writel(val,X) #define ioread8(x) readb(x) #define ioread16(x) readw(x) #define ioread32(x) readl(x) #define iowrite8(val, x) writeb(val, x) #define iowrite16(val, x) writew(val, x) #define iowrite32(val, x) writel(val, x) #define mmiowb() wmb() Loading Loading
arch/blackfin/include/asm/io.h +51 −44 Original line number Diff line number Diff line Loading @@ -31,11 +31,13 @@ static inline unsigned char readb(const volatile void __iomem *addr) unsigned int val; int tmp; __asm__ __volatile__ ("cli %1;\n\t" "NOP; NOP; SSYNC;\n\t" "%0 = b [%2] (z);\n\t" "sti %1;\n\t" : "=d"(val), "=d"(tmp): "a"(addr) __asm__ __volatile__ ( "cli %1;" "NOP; NOP; SSYNC;" "%0 = b [%2] (z);" "sti %1;" : "=d"(val), "=d"(tmp) : "a"(addr) ); return (unsigned char) val; Loading @@ -46,11 +48,13 @@ static inline unsigned short readw(const volatile void __iomem *addr) unsigned int val; int tmp; __asm__ __volatile__ ("cli %1;\n\t" "NOP; NOP; SSYNC;\n\t" "%0 = w [%2] (z);\n\t" "sti %1;\n\t" : "=d"(val), "=d"(tmp): "a"(addr) __asm__ __volatile__ ( "cli %1;" "NOP; NOP; SSYNC;" "%0 = w [%2] (z);" "sti %1;" : "=d"(val), "=d"(tmp) : "a"(addr) ); return (unsigned short) val; Loading @@ -61,12 +65,15 @@ static inline unsigned int readl(const volatile void __iomem *addr) unsigned int val; int tmp; __asm__ __volatile__ ("cli %1;\n\t" "NOP; NOP; SSYNC;\n\t" "%0 = [%2];\n\t" "sti %1;\n\t" : "=d"(val), "=d"(tmp): "a"(addr) __asm__ __volatile__ ( "cli %1;" "NOP; NOP; SSYNC;" "%0 = [%2];" "sti %1;" : "=d"(val), "=d"(tmp) : "a"(addr) ); return val; } Loading Loading @@ -110,12 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define iowrite16_rep(a, s, c) writesw(a, s, c) #define iowrite32_rep(a, s, c) writesl(a, s, c) #define ioread8(X) readb(X) #define ioread16(X) readw(X) #define ioread32(X) readl(X) #define iowrite8(val,X) writeb(val,X) #define iowrite16(val,X) writew(val,X) #define iowrite32(val,X) writel(val,X) #define ioread8(x) readb(x) #define ioread16(x) readw(x) #define ioread32(x) readl(x) #define iowrite8(val, x) writeb(val, x) #define iowrite16(val, x) writew(val, x) #define iowrite32(val, x) writel(val, x) #define mmiowb() wmb() Loading