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Commit 2cae3a1e authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-4.10' of... 

Merge tag 'irqchip-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for 4.10 from Marc Zyngier:

- xylinx interrupt controller made architecture agnostic
  (microblaze, ppc, mips)
- GICv3 ITS now supported on 32bit ARM (mostly useful
  for virtual machines)
- Some arm64 GICv3 cleanups
parents 4e201566 8328255f

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -703,6 +703,7 @@ config ARCH_VIRT 
	select ARM_GIC

	select ARM_GIC_V2M if PCI

	select ARM_GIC_V3

	select ARM_GIC_V3_ITS if PCI

	select ARM_PSCI

	select HAVE_ARM_ARCH_TIMER

arch/arm/include/asm/arch_gicv3.h

+47 −7
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 


#include <linux/io.h>

#include <asm/barrier.h>

#include <asm/cacheflush.h>

#include <asm/cp15.h>



#define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
@@ -230,19 +231,14 @@ static inline void gic_write_bpr1(u32 val) 
 * AArch32, since the syndrome register doesn't provide any information for

 * them.

 * Consequently, the following IO helpers use 32bit accesses.

 *

 * There are only two registers that need 64bit accesses in this driver:

 * - GICD_IROUTERn, contain the affinity values associated to each interrupt.

 *   The upper-word (aff3) will always be 0, so there is no need for a lock.

 * - GICR_TYPER is an ID register and doesn't need atomicity.

 */

static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)

static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)

{

	writel_relaxed((u32)val, addr);

	writel_relaxed((u32)(val >> 32), addr + 4);

}



static inline u64 gic_read_typer(const volatile void __iomem *addr)

static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)

{

	u64 val;
@@ -251,5 +247,49 @@ static inline u64 gic_read_typer(const volatile void __iomem *addr) 
	return val;

}



#define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))



/*

 *  GICD_IROUTERn, contain the affinity values associated to each interrupt.

 *  The upper-word (aff3) will always be 0, so there is no need for a lock.

 */

#define gic_write_irouter(v, c)		__gic_writeq_nonatomic(v, c)



/*

 * GICR_TYPER is an ID register and doesn't need atomicity.

 */

#define gic_read_typer(c)		__gic_readq_nonatomic(c)



/*

 * GITS_BASER - hi and lo bits may be accessed independently.

 */

#define gits_read_baser(c)		__gic_readq_nonatomic(c)

#define gits_write_baser(v, c)		__gic_writeq_nonatomic(v, c)



/*

 * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they

 * won't be being used during any updates and can be changed non-atomically

 */

#define gicr_read_propbaser(c)		__gic_readq_nonatomic(c)

#define gicr_write_propbaser(v, c)	__gic_writeq_nonatomic(v, c)

#define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)

#define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)



/*

 * GITS_TYPER is an ID register and doesn't need atomicity.

 */

#define gits_read_typer(c)		__gic_readq_nonatomic(c)



/*

 * GITS_CBASER - hi and lo bits may be accessed independently.

 */

#define gits_read_cbaser(c)		__gic_readq_nonatomic(c)

#define gits_write_cbaser(v, c)		__gic_writeq_nonatomic(v, c)



/*

 * GITS_CWRITER - hi and lo bits may be accessed independently.

 */

#define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)



#endif /* !__ASSEMBLY__ */

#endif /* !__ASM_ARCH_GICV3_H */

arch/arm64/include/asm/arch_gicv3.h

+31 −30
Original line number Diff line number Diff line
@@ -79,19 +79,10 @@ 


#include <linux/stringify.h>

#include <asm/barrier.h>

#include <asm/cacheflush.h>



#define read_gicreg(r)							\

	({								\

		u64 reg;						\

		asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg));	\

		reg;							\

	})



#define write_gicreg(v,r)						\

	do {								\

		u64 __val = (v);					\

		asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\

	} while (0)

#define read_gicreg			read_sysreg_s

#define write_gicreg			write_sysreg_s



/*

 * Low-level accessors
@@ -102,13 +93,13 @@ 


static inline void gic_write_eoir(u32 irq)

{

	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));

	write_sysreg_s(irq, ICC_EOIR1_EL1);

	isb();

}



static inline void gic_write_dir(u32 irq)

{

	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));

	write_sysreg_s(irq, ICC_DIR_EL1);

	isb();

}
@@ -116,7 +107,7 @@ static inline u64 gic_read_iar_common(void) 
{

	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	irqstat = read_sysreg_s(ICC_IAR1_EL1);

	dsb(sy);

	return irqstat;

}
@@ -132,12 +123,9 @@ static inline u64 gic_read_iar_cavium_thunderx(void) 
{

	u64 irqstat;



	asm volatile(

		"nop;nop;nop;nop\n\t"

		"nop;nop;nop;nop\n\t"

		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"

		"nop;nop;nop;nop"

		: "=r" (irqstat));

	nops(8);

	irqstat = read_sysreg_s(ICC_IAR1_EL1);

	nops(4);

	mb();



	return irqstat;
@@ -145,37 +133,34 @@ static inline u64 gic_read_iar_cavium_thunderx(void) 


static inline void gic_write_pmr(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));

	write_sysreg_s(val, ICC_PMR_EL1);

}



static inline void gic_write_ctlr(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));

	write_sysreg_s(val, ICC_CTLR_EL1);

	isb();

}



static inline void gic_write_grpen1(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));

	write_sysreg_s(val, ICC_GRPEN1_EL1);

	isb();

}



static inline void gic_write_sgi1r(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

	write_sysreg_s(val, ICC_SGI1R_EL1);

}



static inline u32 gic_read_sre(void)

{

	u64 val;



	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	return val;

	return read_sysreg_s(ICC_SRE_EL1);

}



static inline void gic_write_sre(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));

	write_sysreg_s(val, ICC_SRE_EL1);

	isb();

}
@@ -187,5 +172,21 @@ static inline void gic_write_bpr1(u32 val) 
#define gic_read_typer(c)		readq_relaxed(c)

#define gic_write_irouter(v, c)		writeq_relaxed(v, c)



#define gic_flush_dcache_to_poc(a,l)	__flush_dcache_area((a), (l))



#define gits_read_baser(c)		readq_relaxed(c)

#define gits_write_baser(v, c)		writeq_relaxed(v, c)



#define gits_read_cbaser(c)		readq_relaxed(c)

#define gits_write_cbaser(v, c)		writeq_relaxed(v, c)



#define gits_write_cwriter(v, c)	writeq_relaxed(v, c)



#define gicr_read_propbaser(c)		readq_relaxed(c)

#define gicr_write_propbaser(v, c)	writeq_relaxed(v, c)



#define gicr_write_pendbaser(v, c)	writeq_relaxed(v, c)

#define gicr_read_pendbaser(c)		readq_relaxed(c)



#endif /* __ASSEMBLY__ */

#endif /* __ASM_ARCH_GICV3_H */

arch/microblaze/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ config MICROBLAZE 
	select HAVE_MEMBLOCK_NODE_MAP

	select HAVE_OPROFILE

	select IRQ_DOMAIN

	select XILINX_INTC

	select MODULES_USE_ELF_RELA

	select OF

	select OF_EARLY_FLATTREE

arch/microblaze/include/asm/irq.h

+1 −1
Original line number Diff line number Diff line
@@ -16,6 +16,6 @@ struct pt_regs; 
extern void do_IRQ(struct pt_regs *regs);



/* should be defined in each interrupt controller driver */

extern unsigned int get_irq(void);

extern unsigned int xintc_get_irq(void);



#endif /* _ASM_MICROBLAZE_IRQ_H */