drm/msm/dp: implementation to limit the dp link clock frequency

Some targets do not support the DP link clock frequency
greater than 5.4Gbps. These changes limit the link clock frequency
support in the DP driver based on the input from DT property.

Change-Id: Ic76629f9d705d2b9d9e49cd5bc1137dd3ed83fc3
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>