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Commit 2c21d268 authored by Chaotian Jing's avatar Chaotian Jing Committed by Ulf Hansson
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mmc: dt-bindings: update Mediatek MMC bindings 



Add 400Mhz clock source for HS400 mode

Signed-off-by: default avatarChaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 794f1578

Documentation/devicetree/bindings/mmc/mtk-sd.txt

+10 −1
Original line number Diff line number Diff line
@@ -17,6 +17,11 @@ Required properties: 
- vmmc-supply: power to the Core

- vqmmc-supply: power to the IO



Optional properties:

- assigned-clocks: PLL of the source clock

- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock

- hs400-ds-delay: HS400 DS delay setting



Examples:

mmc0: mmc@11230000 {

	compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
@@ -24,9 +29,13 @@ mmc0: mmc@11230000 { 
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;

	vmmc-supply = <&mt6397_vemc_3v3_reg>;

	vqmmc-supply = <&mt6397_vio18_reg>;

	clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

	clocks = <&pericfg CLK_PERI_MSDC30_0>,

	         <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

	clock-names = "source", "hclk";

	pinctrl-names = "default", "state_uhs";

	pinctrl-0 = <&mmc0_pins_default>;

	pinctrl-1 = <&mmc0_pins_uhs>;

	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;

	hs400-ds-delay = <0x14015>;

};