plat-orion: share time handling code (2bac1de2) · Commits · e / devices / android_kernel_fairphone_FP4

arch/arm/mach-orion/Makefile

+1 −1

Original line number	Diff line number	Diff line
		obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
		obj-y += common.o addr-map.o pci.o gpio.o irq.o
		obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
		obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
		obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o

arch/arm/mach-orion/common.c

+16 −0

Original line number	Diff line number	Diff line
		@@ -23,8 +23,11 @@
		#include <asm/timex.h>
		#include <asm/mach/arch.h>
		#include <asm/mach/map.h>
		#include <asm/mach/time.h>
		#include <asm/arch/hardware.h>
		#include <asm/arch/orion.h>
		#include <asm/arch/platform.h>
		#include <asm/plat-orion/time.h>
		#include "common.h"

		/*****************************************************************************
		@@ -295,6 +298,19 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
		platform_device_register(&orion_sata);
		}

		/*****************************************************************************
		* Time handling
		****************************************************************************/

		static void orion_timer_init(void)
		{
		orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK);
		}

		struct sys_timer orion_timer = {
		.init = orion_timer_init,
		};

		/*****************************************************************************
		* General
		****************************************************************************/

arch/arm/mach-orion/common.h

+1 −5

Original line number	Diff line number	Diff line
		@@ -8,6 +8,7 @@
		void __init orion_map_io(void);
		void __init orion_init_irq(void);
		void __init orion_init(void);
		extern struct sys_timer orion_timer;

		/*
		* Enumerations and functions for Orion windows mapping. Used by Orion core
		@@ -56,11 +57,6 @@ struct pci_bus orion_pci_sys_scan_bus(int nr, struct pci_sys_data sys);
		void __init orion_gpio_set_valid_pins(u32 pins);
		void gpio_display(void); /* debug */

		/*
		* Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
		*/
		extern struct sys_timer orion_timer;

		/*
		* Pull in Orion Ethernet platform_data, used by machine-setup
		*/

arch/arm/plat-orion/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -2,7 +2,7 @@
		# Makefile for the linux kernel.
		#

		obj-y := irq.o pcie.o
		obj-y := irq.o pcie.o time.o
		obj-m :=
		obj-n :=
		obj- :=

arch/arm/mach-orion/time.c→arch/arm/plat-orion/time.c

+203 −0

Original line number	Diff line number	Diff line
		/*
		* arch/arm/mach-orion/time.c
		* arch/arm/plat-orion/time.c
		*
		* Core time functions for Marvell Orion System On Chip
		*
		* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
		* Marvell Orion SoC timer handling.
		*
		* This file is licensed under the terms of the GNU General Public
		* License version 2. This program is licensed "as is" without any
		* warranty of any kind, whether express or implied.
		*
		* Timer 0 is used as free-running clocksource, while timer 1 is
		* used as clock_event_device.
		*/

		#include <linux/kernel.h>
		@@ -15,32 +16,34 @@
		#include <linux/interrupt.h>
		#include <linux/irq.h>
		#include <asm/mach/time.h>
		#include <asm/arch/orion.h>
		#include "common.h"
		#include <asm/arch/hardware.h>

		/*
		* Timer0: clock_event_device, Tick.
		* Timer1: clocksource, Free running.
		* WatchDog: Not used.
		*
		* Timers are counting down.
		* Number of timer ticks per jiffy.
		*/
		#define CLOCKEVENT 0
		#define CLOCKSOURCE 1
		static u32 ticks_per_jiffy;


		/*
		* Timers bits
		* Timer block registers.
		*/
		#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
		#define TIMER_EN(x) (1 << ((x) * 2))
		#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
		#define BRIDGE_INT_TIMER_WD (1 << 3)
		#define TIMER_WD_EN (1 << 4)
		#define TIMER_WD_RELOAD_EN (1 << 5)
		#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
		#define TIMER0_EN 0x0001
		#define TIMER0_RELOAD_EN 0x0002
		#define TIMER1_EN 0x0004
		#define TIMER1_RELOAD_EN 0x0008
		#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
		#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
		#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
		#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)


		/*
		* Clocksource handling.
		*/
		static cycle_t orion_clksrc_read(void)
		{
		return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
		return 0xffffffff - readl(TIMER0_VAL);
		}

		static struct clocksource orion_clksrc = {
		@@ -52,10 +55,16 @@ static struct clocksource orion_clksrc = {
		.flags = CLOCK_SOURCE_IS_CONTINUOUS,
		};



		/*
		* Clockevent handling.
		*/
		static int
		orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
		{
		unsigned long flags;
		u32 u;

		if (delta == 0)
		return -ETIME;
		@@ -63,21 +72,25 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
		local_irq_save(flags);

		/*
		* Clear and enable timer interrupt bit
		* Clear and enable clockevent timer interrupt.
		*/
		orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
		orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
		writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);

		u = readl(BRIDGE_MASK);
		u \|= BRIDGE_INT_TIMER1;
		writel(u, BRIDGE_MASK);

		/*
		* Setup new timer value
		* Setup new clockevent timer value.
		*/
		orion_write(TIMER_VAL(CLOCKEVENT), delta);
		writel(delta, TIMER1_VAL);

		/*
		* Disable auto reload and kickoff the timer
		* Enable the timer.
		*/
		orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
		orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
		u = readl(TIMER_CTRL);
		u = (u & ~TIMER1_RELOAD_EN) \| TIMER1_EN;
		writel(u, TIMER_CTRL);

		local_irq_restore(flags);

		@@ -88,34 +101,52 @@ static void
		orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
		{
		unsigned long flags;
		u32 u;

		local_irq_save(flags);

		if (mode == CLOCK_EVT_MODE_PERIODIC) {
		/*
		* Setup latch cycles in timer and enable reload interrupt.
		* Setup timer to fire at 1/HZ intervals.
		*/
		writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
		writel(ticks_per_jiffy - 1, TIMER1_VAL);

		/*
		* Enable timer interrupt.
		*/
		u = readl(BRIDGE_MASK);
		writel(u \| BRIDGE_INT_TIMER1, BRIDGE_MASK);

		/*
		* Enable timer.
		*/
		orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
		orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
		orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
		orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) \|
		TIMER_EN(CLOCKEVENT));
		u = readl(TIMER_CTRL);
		writel(u \| TIMER1_EN \| TIMER1_RELOAD_EN, TIMER_CTRL);
		} else {
		/*
		* Disable timer and interrupt
		* Disable timer.
		*/
		orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
		orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
		orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) \|
		TIMER_EN(CLOCKEVENT));
		}
		u = readl(TIMER_CTRL);
		writel(u & ~TIMER1_EN, TIMER_CTRL);

		/*
		* Disable timer interrupt.
		*/
		u = readl(BRIDGE_MASK);
		writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);

		/*
		* ACK pending timer interrupt.
		*/
		writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);

		}
		local_irq_restore(flags);
		}

		static struct clock_event_device orion_clkevt = {
		.name = "orion_tick",
		.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
		.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
		.shift = 32,
		.rating = 300,
		.cpumask = CPU_MASK_CPU0,
		@@ -126,10 +157,11 @@ static struct clock_event_device orion_clkevt = {
		static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
		{
		/*
		* Clear cause bit and do event
		* ACK timer interrupt and call event handler.
		*/
		orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
		writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
		orion_clkevt.event_handler(&orion_clkevt);

		return IRQ_HANDLED;
		}

		@@ -139,43 +171,33 @@ static struct irqaction orion_timer_irq = {
		.handler = orion_timer_interrupt
		};

		static void orion_timer_init(void)
		void __init orion_time_init(unsigned int irq, unsigned int tclk)
		{
		/*
		* Setup clocksource free running timer (no interrupt on reload)
		*/
		orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
		orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
		orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
		orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) \|
		TIMER_EN(CLOCKSOURCE));
		u32 u;

		/*
		* Register clocksource
		*/
		orion_clksrc.mult =
		clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
		ticks_per_jiffy = (tclk + HZ/2) / HZ;

		clocksource_register(&orion_clksrc);

		/*
		* Connect and enable tick handler
		* Setup free-running clocksource timer (interrupts
		* disabled.)
		*/
		setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
		writel(0xffffffff, TIMER0_VAL);
		writel(0xffffffff, TIMER0_RELOAD);
		u = readl(BRIDGE_MASK);
		writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
		u = readl(TIMER_CTRL);
		writel(u \| TIMER0_EN \| TIMER0_RELOAD_EN, TIMER_CTRL);
		orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
		clocksource_register(&orion_clksrc);


		/*
		* Register clockevent
		* Setup clockevent timer (interrupt-driven.)
		*/
		orion_clkevt.mult =
		div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
		orion_clkevt.max_delta_ns =
		clockevent_delta2ns(0xfffffffe, &orion_clkevt);
		orion_clkevt.min_delta_ns =
		clockevent_delta2ns(1, &orion_clkevt);

		setup_irq(irq, &orion_timer_irq);
		orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
		orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
		orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
		clockevents_register_device(&orion_clkevt);
		}

		struct sys_timer orion_timer = {
		.init = orion_timer_init,
		};