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Commit 2b2874ef authored by Oscar Mateo's avatar Oscar Mateo Committed by Mika Kuoppala
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drm/i915/icl: Enable RC6 and RPS in Gen11 



AFAICT, once the new interrupt is in place, the rest should behave the
same as Gen10.

v2: Update ring frequencies (Sagar)
v3: Rebase.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarMichel Thierry <michel.thierry@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180405140052.10682-5-mika.kuoppala@linux.intel.com
parent 96606f3b

drivers/gpu/drm/i915/i915_debugfs.c

+5 −5
Original line number Diff line number Diff line
@@ -1215,20 +1215,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);

			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));



		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);

			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));



		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

			    rp_state_cap >> 0) & 0xff;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);

			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));

		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1811,7 +1811,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 


	min_gpu_freq = rps->min_freq;

	max_gpu_freq = rps->max_freq;

	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {

	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {

		/* Convert GT frequency to 50 HZ units */

		min_gpu_freq /= GEN9_FREQ_SCALER;

		max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -1827,7 +1827,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 
		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",

			   intel_gpu_freq(dev_priv, (gpu_freq *

						     (IS_GEN9_BC(dev_priv) ||

						      IS_CANNONLAKE(dev_priv) ?

						      INTEL_GEN(dev_priv) >= 10 ?

						      GEN9_FREQ_SCALER : 1))),

			   ((ia_freq >> 0) & 0xff) * 100,

			   ((ia_freq >> 8) & 0xff) * 100);

drivers/gpu/drm/i915/intel_pm.c

+4 −6
Original line number Diff line number Diff line
@@ -6572,7 +6572,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) 


	rps->efficient_freq = rps->rp1_freq;

	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||

	    IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {

	    IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {

		u32 ddcc_status = 0;



		if (sandybridge_pcode_read(dev_priv,
@@ -6585,7 +6585,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) 
					rps->max_freq);

	}



	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {

	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {

		/* Store the frequency values in 16.66 MHZ units, which is

		 * the natural hardware unit for SKL

		 */
@@ -6923,7 +6923,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) 


	min_gpu_freq = rps->min_freq;

	max_gpu_freq = rps->max_freq;

	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {

	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {

		/* Convert GT frequency to 50 HZ units */

		min_gpu_freq /= GEN9_FREQ_SCALER;

		max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -6938,7 +6938,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) 
		const int diff = max_gpu_freq - gpu_freq;

		unsigned int ia_freq = 0, ring_freq = 0;



		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {

		if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {

			/*

			 * ring_freq = 2 * GT. ring_freq is in 100MHz units

			 * No floor required for ring frequency on SKL.
@@ -8144,8 +8144,6 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) 
		cherryview_enable_rps(dev_priv);

	} else if (IS_VALLEYVIEW(dev_priv)) {

		valleyview_enable_rps(dev_priv);

	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {

		/* TODO */

	} else if (INTEL_GEN(dev_priv) >= 9) {

		gen9_enable_rps(dev_priv);

	} else if (IS_BROADWELL(dev_priv)) {