Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2b19d17f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: fix typo in PG flags



s/CG/PG/ in the GFX powergating flag name.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9a716778
Loading
Loading
Loading
Loading
+3 −3
Original line number Diff line number Diff line
@@ -5558,7 +5558,7 @@ static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
{
	u32 data, orig;

	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
		orig = data = RREG32(RLC_PG_CNTL);
		data |= GFX_PG_ENABLE;
		if (orig != data)
@@ -5822,7 +5822,7 @@ static void cik_init_pg(struct radeon_device *rdev)
	if (rdev->pg_flags) {
		cik_enable_sck_slowdown_on_pu(rdev, true);
		cik_enable_sck_slowdown_on_pd(rdev, true);
		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
			cik_init_gfx_cgpg(rdev);
			cik_enable_cp_pg(rdev, true);
			cik_enable_gds_pg(rdev, true);
@@ -5836,7 +5836,7 @@ static void cik_fini_pg(struct radeon_device *rdev)
{
	if (rdev->pg_flags) {
		cik_update_gfx_pg(rdev, false);
		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
			cik_enable_cp_pg(rdev, false);
			cik_enable_gds_pg(rdev, false);
		}
+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ extern int radeon_aspm;
#define RADEON_CG_SUPPORT_HDP_MGCG		(1 << 16)

/* PG flags */
#define RADEON_PG_SUPPORT_GFX_CG		(1 << 0)
#define RADEON_PG_SUPPORT_GFX_PG		(1 << 0)
#define RADEON_PG_SUPPORT_GFX_SMG		(1 << 1)
#define RADEON_PG_SUPPORT_GFX_DMG		(1 << 2)
#define RADEON_PG_SUPPORT_UVD			(1 << 3)
+3 −3
Original line number Diff line number Diff line
@@ -2391,7 +2391,7 @@ int radeon_asic_init(struct radeon_device *rdev)
				RADEON_CG_SUPPORT_HDP_LS |
				RADEON_CG_SUPPORT_HDP_MGCG;
			rdev->pg_flags = 0 |
				/*RADEON_PG_SUPPORT_GFX_CG | */
				/*RADEON_PG_SUPPORT_GFX_PG | */
				RADEON_PG_SUPPORT_SDMA;
			break;
		case CHIP_OLAND:
@@ -2480,7 +2480,7 @@ int radeon_asic_init(struct radeon_device *rdev)
				RADEON_CG_SUPPORT_HDP_LS |
				RADEON_CG_SUPPORT_HDP_MGCG;
			rdev->pg_flags = 0;
				/*RADEON_PG_SUPPORT_GFX_CG |
				/*RADEON_PG_SUPPORT_GFX_PG |
				RADEON_PG_SUPPORT_GFX_SMG |
				RADEON_PG_SUPPORT_GFX_DMG |
				RADEON_PG_SUPPORT_UVD |
@@ -2508,7 +2508,7 @@ int radeon_asic_init(struct radeon_device *rdev)
				RADEON_CG_SUPPORT_HDP_LS |
				RADEON_CG_SUPPORT_HDP_MGCG;
			rdev->pg_flags = 0;
				/*RADEON_PG_SUPPORT_GFX_CG |
				/*RADEON_PG_SUPPORT_GFX_PG |
				RADEON_PG_SUPPORT_GFX_SMG |
				RADEON_PG_SUPPORT_UVD |
				RADEON_PG_SUPPORT_VCE |
+2 −2
Original line number Diff line number Diff line
@@ -4894,7 +4894,7 @@ static void si_enable_gfx_cgpg(struct radeon_device *rdev,
{
	u32 tmp;

	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
		tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
		WREG32(RLC_TTOP_D, tmp);

@@ -5416,7 +5416,7 @@ static void si_init_pg(struct radeon_device *rdev)
			si_init_dma_pg(rdev);
		}
		si_init_ao_cu_mask(rdev);
		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
			si_init_gfx_cgpg(rdev);
		}
		si_enable_dma_pg(rdev, true);