Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2a929436 authored by Mark Nelson's avatar Mark Nelson Committed by Paul Mackerras
Browse files

powerpc: Add new CPU feature: CPU_FTR_CP_USE_DCBTZ 



Add a new CPU feature bit, CPU_FTR_CP_USE_DCBTZ, to be added to the
64bit powerpc chips that benefit from having dcbt and dcbz
instructions used in their memory copy routines.

This will be used in a subsequent patch that updates copy_4K_page().
The new bit is added to Cell, PPC970 and Power4 because they show
better performance with the new copy_4K_page() when dcbt and dcbz
instructions are used.

Signed-off-by: default avatarMark Nelson <markn@au1.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 1b3c83e6

arch/powerpc/include/asm/cputable.h

+6 −3
Original line number Original line Diff line number Diff line
@@ -193,6 +193,7 @@ extern const char *powerpc_base_platform; 
#define CPU_FTR_NO_SLBIE_B		LONG_ASM_CONST(0x0008000000000000)

#define CPU_FTR_NO_SLBIE_B		LONG_ASM_CONST(0x0008000000000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0010000000000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0010000000000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0020000000000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0020000000000000)

#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0040000000000000)





#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__
@@ -388,10 +389,11 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_MMCRA | CPU_FTR_CTRL)

	    CPU_FTR_MMCRA | CPU_FTR_CTRL)

#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA)

	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)

#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \

	    CPU_FTR_CP_USE_DCBTZ)

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -412,7 +414,8 @@ extern const char *powerpc_base_platform; 
#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)

	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ)

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \