Commit 2a865745 authored Feb 15, 2019 by Chinmay Sawarkar

ARM: dts: msm: Set core clock config to zero



This will ensure that System and AXI clocks are always provided
to the MVP_CORE. This register must be set at Cold & Warm boot,
before PIL load.

CRs-Fixed: 2384822
Change-Id: I71a0b3b191134e9bf6abbcac0472f004fc3638eb
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>

parent e222d4df

arch/arm64/boot/dts/qcom/kona-vidc.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,8 @@
		<&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>;
		reset-names = "video_axi_reset", "video_core_reset";

		qcom,reg-presets = <0xB0088 0x0>;

		/* Buses */
		bus_cnoc {
		compatible = "qcom,msm-vidc,bus";