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Commit 2a451bfa authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
Browse files

ARM: sun8i: v3s: enable SPI 



Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller
at PC bank. The controller itself is identical to the one in H3 SoC.

Add device tree node and the only pinmux node for it.

Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi
early sample.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 87ac8e18

arch/arm/boot/dts/sun8i-v3s.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -234,6 +234,11 @@ 
				drive-strength = <30>;

				bias-pull-up;

			};



			spi0_pins: spi0 {

				pins = "PC0", "PC1", "PC2", "PC3";

				function = "spi0";

			};

		};



		timer@01c20c00 {
@@ -314,6 +319,20 @@ 
			#size-cells = <0>;

		};



		spi0: spi@1c68000 {

			compatible = "allwinner,sun8i-h3-spi";

			reg = <0x01c68000 0x1000>;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;

			clock-names = "ahb", "mod";

			pinctrl-names = "default";

			pinctrl-0 = <&spi0_pins>;

			resets = <&ccu RST_BUS_SPI0>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		gic: interrupt-controller@01c81000 {

			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";

			reg = <0x01c81000 0x1000>,