[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 (2a21c730) · Commits · e / devices / android_kernel_fairphone_FP4

arch/mips/Kconfig

+22 −0

Original line number	Original line	Diff line number	Diff line
	@@ -894,6 +894,16 @@ choice
	prompt "CPU type"		prompt "CPU type"
	default CPU_R4X00		default CPU_R4X00

			config CPU_LOONGSON2
			bool "Loongson 2"
			depends on SYS_HAS_CPU_LOONGSON2
			select CPU_SUPPORTS_32BIT_KERNEL
			select CPU_SUPPORTS_64BIT_KERNEL
			select CPU_SUPPORTS_HIGHMEM
			help
			The Loongson 2E processor implements the MIPS III instruction set
			with many extensions.

	config CPU_MIPS32_R1		config CPU_MIPS32_R1
	bool "MIPS32 Release 1"		bool "MIPS32 Release 1"
	depends on SYS_HAS_CPU_MIPS32_R1		depends on SYS_HAS_CPU_MIPS32_R1
	@@ -1104,6 +1114,9 @@ config CPU_SB1

	endchoice		endchoice

			config SYS_HAS_CPU_LOONGSON2
			bool

	config SYS_HAS_CPU_MIPS32_R1		config SYS_HAS_CPU_MIPS32_R1
	bool		bool

	@@ -1438,6 +1451,15 @@ config CPU_HAS_SMARTMIPS
	config CPU_HAS_WB		config CPU_HAS_WB
	bool		bool

			config 64BIT_CONTEXT
			bool "Save 64bit integer registers"
			depends on 32BIT && CPU_LOONGSON2
			help
			Loongson2 CPU is 64bit , when used in 32BIT mode, its integer
			registers can still be accessed as 64bit, mainly for multimedia
			instructions. We must have all 64bit save/restored to make sure
			those instructions to get correct result.

	#		#
	# Vectored interrupt mode is an R2 feature		# Vectored interrupt mode is an R2 feature
	#		#

arch/mips/Makefile

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
	cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap		cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
	cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap		cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
	cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap		cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
			cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
	cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \		cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
	-Wa,-mips32 -Wa,--trap		-Wa,-mips32 -Wa,--trap
	cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \		cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \

arch/mips/kernel/Makefile

+7 −6

Original line number	Original line	Diff line number	Diff line
	@@ -14,14 +14,15 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
	obj-$(CONFIG_STACKTRACE) += stacktrace.o		obj-$(CONFIG_STACKTRACE) += stacktrace.o
	obj-$(CONFIG_MODULES) += mips_ksyms.o module.o		obj-$(CONFIG_MODULES) += mips_ksyms.o module.o

			obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o
			obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
			obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o		obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
	obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
	obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o
			obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o
	@@ -29,9 +30,9 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
	obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
	obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o		obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o

	obj-$(CONFIG_SMP) += smp.o		obj-$(CONFIG_SMP) += smp.o

arch/mips/kernel/cpu-probe.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -485,6 +485,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
	MIPS_CPU_LLSC;		MIPS_CPU_LLSC;
	c->tlbsize = 64;		c->tlbsize = 64;
	break;		break;
			case PRID_IMP_LOONGSON2:
			c->cputype = CPU_LOONGSON2;
			c->isa_level = MIPS_CPU_ISA_III;
			c->options = R4K_OPTS \|
			MIPS_CPU_FPU \| MIPS_CPU_LLSC \|
			MIPS_CPU_32FPR;
			c->tlbsize = 64;
			break;
	}		}
	}		}

arch/mips/kernel/proc.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -83,6 +83,7 @@ static const char *cpu_name[] = {
	[CPU_VR4181A] = "NEC VR4181A",		[CPU_VR4181A] = "NEC VR4181A",
	[CPU_SR71000] = "Sandcraft SR71000",		[CPU_SR71000] = "Sandcraft SR71000",
	[CPU_PR4450] = "Philips PR4450",		[CPU_PR4450] = "Philips PR4450",
			[CPU_LOONGSON2] = "ICT Loongson-2",
	};		};