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Commit 2a18ce9e authored by Ritesh Kumar's avatar Ritesh Kumar
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teckpack: disp: pll: Improve logging for 10nm dsi pll



Avoid warning of slave pll unavailable for chipsets
not having slave pll.

Change-Id: Id32af235f2fbefa4869b5c8236436e8e6ed84d60
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent 88b222ad
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