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Commit 2a073f89 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
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drm/i915/bxt: map GTT as uncached 



On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.

v2:
- add comment explaining how the problem with WC mapping manifests
  (Daniel)

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8232edb5

drivers/gpu/drm/i915/i915_gem_gtt.c

+11 −1
Original line number Diff line number Diff line
@@ -2253,6 +2253,16 @@ static int ggtt_probe_common(struct drm_device *dev, 
	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +

		(pci_resource_len(dev->pdev, 0) / 2);



	/*

	 * On BXT writes larger than 64 bit to the GTT pagetable range will be

	 * dropped. For WC mappings in general we have 64 byte burst writes

	 * when the WC buffer is flushed, so we can't use it, but have to

	 * resort to an uncached mapping. The WC issue is easily caught by the

	 * readback check when writing GTT PTE entries.

	 */

	if (IS_BROXTON(dev))

		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);

	else

		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);

	if (!dev_priv->gtt.gsm) {

		DRM_ERROR("Failed to map the gtt page table\n");