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Commit 29dbe3bc authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: allocate PPLLs from low to high 



The order shouldn't matter, but there have been problems
reported on certain older asics.  This behaves more
like the original code before the PPLL allocation
rework.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc:  Markus Trippelsdorf <markus@trippelsdorf.de>
parent cd23492a

drivers/gpu/drm/radeon/atombios_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -1690,10 +1690,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
		}

		/* all other cases */

		pll_in_use = radeon_get_pll_use_mask(crtc);

		if (!(pll_in_use & (1 << ATOM_PPLL2)))

			return ATOM_PPLL2;

		if (!(pll_in_use & (1 << ATOM_PPLL1)))

			return ATOM_PPLL1;

		if (!(pll_in_use & (1 << ATOM_PPLL2)))

			return ATOM_PPLL2;

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else {
@@ -1715,10 +1715,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
			}

			/* all other cases */

			pll_in_use = radeon_get_pll_use_mask(crtc);

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			DRM_ERROR("unable to allocate a PPLL\n");

			return ATOM_PPLL_INVALID;

		} else {