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Commit 29c7f3e6 authored by Kazuya Mizuguchi's avatar Kazuya Mizuguchi Committed by Felipe Balbi
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usb: renesas_usbhs: Fix DMAC sequence for receiving zero-length packet 



The DREQE bit of the DnFIFOSEL should be set to 1 after the DE bit of
USB-DMAC on R-Car SoCs is set to 1 after the USB-DMAC received a
zero-length packet. Otherwise, a transfer completion interruption
of USB-DMAC doesn't happen. Even if the driver changes the sequence,
normal operations (transmit/receive without zero-length packet) will
not cause any side-effects. So, this patch fixes the sequence anyway.

Signed-off-by: default avatarKazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[shimoda: revise the commit log]
Fixes: e73a9891 ("usb: renesas_usbhs: add DMAEngine support")
Cc: <stable@vger.kernel.org> # v3.1+
Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent ab219221

drivers/usb/renesas_usbhs/fifo.c

+1 −1
Original line number Diff line number Diff line
@@ -857,9 +857,9 @@ static void xfer_work(struct work_struct *work) 
		fifo->name, usbhs_pipe_number(pipe), pkt->length, pkt->zero);



	usbhs_pipe_running(pipe, 1);

	usbhsf_dma_start(pipe, fifo);

	usbhs_pipe_set_trans_count_if_bulk(pipe, pkt->trans);

	dma_async_issue_pending(chan);

	usbhsf_dma_start(pipe, fifo);

	usbhs_pipe_enable(pipe);



xfer_work_end: