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Commit 29390d27 authored by Yixun Lan's avatar Yixun Lan Committed by Kevin Hilman
Browse files

ARM64: dts: meson-axg: add ethernet mac controller 



Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.

Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 8ae4284e

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+53 −0
Original line number Diff line number Diff line
@@ -178,6 +178,19 @@ 
			};

		};



		ethmac: ethernet@ff3f0000 {

			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";

			reg = <0x0 0xff3f0000 0x0 0x10000

				0x0 0xff634540 0x0 0x8>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "macirq";

			clocks = <&clkc CLKID_ETH>,

				 <&clkc CLKID_FCLK_DIV2>,

				 <&clkc CLKID_MPLL2>;

			clock-names = "stmmaceth", "clkin0", "clkin1";

			status = "disabled";

		};



		gic: interrupt-controller@ffc01000 {

			compatible = "arm,gic-400";

			reg = <0x0 0xffc01000 0 0x1000>,
@@ -238,6 +251,46 @@ 
					gpio-ranges = <&pinctrl_periphs 0 0 86>;

				};



				eth_rgmii_x_pins: eth-x-rgmii {

					mux {

						groups = "eth_mdio_x",

						       "eth_mdc_x",

						       "eth_rgmii_rx_clk_x",

						       "eth_rx_dv_x",

						       "eth_rxd0_x",

						       "eth_rxd1_x",

						       "eth_rxd2_rgmii",

						       "eth_rxd3_rgmii",

						       "eth_rgmii_tx_clk",

						       "eth_txen_x",

						       "eth_txd0_x",

						       "eth_txd1_x",

						       "eth_txd2_rgmii",

						       "eth_txd3_rgmii";

						function = "eth";

					};

				};



				eth_rgmii_y_pins: eth-y-rgmii {

					mux {

						groups = "eth_mdio_y",

						       "eth_mdc_y",

						       "eth_rgmii_rx_clk_y",

						       "eth_rx_dv_y",

						       "eth_rxd0_y",

						       "eth_rxd1_y",

						       "eth_rxd2_rgmii",

						       "eth_rxd3_rgmii",

						       "eth_rgmii_tx_clk",

						       "eth_txen_y",

						       "eth_txd0_y",

						       "eth_txd1_y",

						       "eth_txd2_rgmii",

						       "eth_txd3_rgmii";

						function = "eth";

					};

				};



				pwm_a_a_pins: pwm_a_a {

					mux {

						groups = "pwm_a_a";