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Commit 28e460b0 authored by Jes Sorensen's avatar Jes Sorensen Committed by Kalle Valo
Browse files

rtl8xxxu: Adjust AFE crystal value on 8192eu 



Adjust AFE before enabling PLL on 8192eu, probably also needed for
8723bu.

Signed-off-by: default avatarJes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent f991f4e9

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

+39 −0
Original line number Diff line number Diff line
@@ -7093,6 +7093,41 @@ static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) 


#endif



/*

 * This is needed for 8723bu as well, presumable

 */

static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)

{

	u8 val8;

	u32 val32;



	/*

	 * 40Mhz crystal source, MAC 0x28[2]=0

	 */

	val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);

	val8 &= 0xfb;

	rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);



	val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);

	val32 &= 0xfffffc7f;

	rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);



	/*

	 * 92e AFE parameter

	 * AFE PLL KVCO selection, MAC 0x28[6]=1

	 */

	val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);

	val8 &= 0xbf;

	rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);



	/*

	 * AFE PLL KVCO selection, MAC 0x78[21]=0

	 */

	val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);

	val32 &= 0xffdfffff;

	rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);

}



static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)

{

	u16 val16;
@@ -7115,6 +7150,10 @@ static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) 
		rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);

	}



	/*

	 * Adjust AFE before enabling PLL

	 */

	rtl8192e_crystal_afe_adjust(priv);

	rtl8192e_disabled_to_emu(priv);



	ret = rtl8192e_emu_to_active(priv);

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -109,6 +109,9 @@ 
#define  AFE_XTAL_GATE_DIG		BIT(17)

#define  AFE_XTAL_BT_GATE		BIT(20)



/*

 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu

 */

#define REG_AFE_PLL_CTRL		0x0028

#define  AFE_PLL_ENABLE			BIT(0)

#define  AFE_PLL_320_ENABLE		BIT(1)
@@ -192,6 +195,7 @@ 
						   control */

#define  MULTI_GPS_FUNC_EN		BIT(22)	/* GPS function enable */



#define REG_AFE_CTRL4			0x0078	/* 8192eu/8723bu */

#define REG_LDO_SW_CTRL			0x007c	/* 8192eu */



#define REG_MCU_FW_DL			0x0080