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Commit 287d2ac3 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next 

- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes

* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
  amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
  drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
  drm/amd/display: fix dereferencing possible ERR_PTR()
  drm/amd/display: Refine disable VGA
  drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
  drm/radeon: Don't turn off DP sink when disconnected
  drm/amd/pp: Rename file name cz_* to smu8_*
  drm/amd/pp: Replace function/struct name cz_* with smu8_*
  drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
  drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
  drm/amd/pp: Remove dead header file pp_asicblocks.h
  drm/amd/pp: Delete dead code on cz_clockpowergating.c
  drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
  drm/amdgpu: Remove wrapper layer of smu ip functions
  drm/amdgpu: Don't compared ip_block_type with ip_block_index
  drm/amdgpu: Plus NULL function pointer check
  drm/amd/pp: Move helper functions to smu_help.c
  drm/amd/pp: Replace rv_* with smu10_*
  drm/amd/pp: Fix function parameter not correct
  drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
  ...
parents 963976cf 6da2b933

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -87,8 +87,7 @@ amdgpu-y += \ 


# add SMC block

amdgpu-y += \

	amdgpu_dpm.o \

	amdgpu_powerplay.o

	amdgpu_dpm.o



# add DCE block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+7 −5
Original line number Diff line number Diff line
@@ -441,7 +441,7 @@ struct amdgpu_sa_bo { 
void amdgpu_gem_force_release(struct amdgpu_device *adev);

int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,

			     int alignment, u32 initial_domain,

			     u64 flags, bool kernel,

			     u64 flags, enum ttm_bo_type type,

			     struct reservation_object *resv,

			     struct drm_gem_object **obj);
@@ -1081,8 +1081,6 @@ struct amdgpu_wb { 
int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);



void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);



/*

 * SDMA

 */
@@ -1395,9 +1393,7 @@ enum amd_hw_ip_block_type { 
#define HWIP_MAX_INSTANCE	6



struct amd_powerplay {

	struct cgs_device *cgs_device;

	void *pp_handle;

	const struct amd_ip_funcs *ip_funcs;

	const struct amd_pm_funcs *pp_funcs;

};
@@ -1632,6 +1628,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 
			uint32_t acc_flags);

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags);

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);



u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
@@ -1655,6 +1654,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)



#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))

#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))



#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)

#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+3 −2
Original line number Diff line number Diff line
@@ -221,8 +221,9 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 
	uint64_t gpu_addr_tmp = 0;

	void *cpu_ptr_tmp = NULL;



	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,

			AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, &bo);

	r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,

			     AMDGPU_GEM_CREATE_CPU_GTT_USWC, ttm_bo_type_kernel,

			     NULL, &bo);

	if (r) {

		dev_err(adev->dev,

			"failed to allocate BO for amdkfd (%d)\n", r);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+2 −2
Original line number Diff line number Diff line
@@ -997,8 +997,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 
	pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",

			va, size, domain_string(alloc_domain));



	ret = amdgpu_bo_create(adev, size, byte_align, false,

				alloc_domain, alloc_flags, NULL, NULL, &bo);

	ret = amdgpu_bo_create(adev, size, byte_align,

				alloc_domain, alloc_flags, ttm_bo_type_device, NULL, &bo);

	if (ret) {

		pr_debug("Failed to create BO on domain %s. ret %d\n",

				domain_string(alloc_domain), ret);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+91 −4
Original line number Diff line number Diff line
@@ -114,6 +114,9 @@ union igp_info { 
	struct atom_integrated_system_info_v1_11 v11;

};



union umc_info {

	struct atom_umc_info_v3_1 v31;

};

/*

 * Return vram width from integrated system info table, if available,

 * or 0 if not.
@@ -143,6 +146,94 @@ int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev) 
	return 0;

}



static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,

					       int atom_mem_type)

{

	int vram_type;



	if (adev->flags & AMD_IS_APU) {

		switch (atom_mem_type) {

		case Ddr2MemType:

		case LpDdr2MemType:

			vram_type = AMDGPU_VRAM_TYPE_DDR2;

			break;

		case Ddr3MemType:

		case LpDdr3MemType:

			vram_type = AMDGPU_VRAM_TYPE_DDR3;

			break;

		case Ddr4MemType:

		case LpDdr4MemType:

			vram_type = AMDGPU_VRAM_TYPE_DDR4;

			break;

		default:

			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

			break;

		}

	} else {

		switch (atom_mem_type) {

		case ATOM_DGPU_VRAM_TYPE_GDDR5:

			vram_type = AMDGPU_VRAM_TYPE_GDDR5;

			break;

		case ATOM_DGPU_VRAM_TYPE_HBM:

			vram_type = AMDGPU_VRAM_TYPE_HBM;

			break;

		default:

			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

			break;

		}

	}



	return vram_type;

}

/*

 * Return vram type from either integrated system info table

 * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not

 */

int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index;

	u16 data_offset, size;

	union igp_info *igp_info;

	union umc_info *umc_info;

	u8 frev, crev;

	u8 mem_type;



	if (adev->flags & AMD_IS_APU)

		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						    integratedsysteminfo);

	else

		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						    umc_info);

	if (amdgpu_atom_parse_data_header(mode_info->atom_context,

					  index, &size,

					  &frev, &crev, &data_offset)) {

		if (adev->flags & AMD_IS_APU) {

			igp_info = (union igp_info *)

				(mode_info->atom_context->bios + data_offset);

			switch (crev) {

			case 11:

				mem_type = igp_info->v11.memorytype;

				return convert_atom_mem_type_to_vram_type(adev, mem_type);

			default:

				return 0;

			}

		} else {

			umc_info = (union umc_info *)

				(mode_info->atom_context->bios + data_offset);

			switch (crev) {

			case 1:

				mem_type = umc_info->v31.vram_type;

				return convert_atom_mem_type_to_vram_type(adev, mem_type);

			default:

				return 0;

			}

		}

	}



	return 0;

}



union firmware_info {

	struct atom_firmware_info_v3_1 v31;

};
@@ -151,10 +242,6 @@ union smu_info { 
	struct atom_smu_info_v3_1 v31;

};



union umc_info {

	struct atom_umc_info_v3_1 v31;

};



int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;