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Commit 287b4cc4 authored by Vipin Deep Kaur's avatar Vipin Deep Kaur
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ARM: dts: msm: Configure SMMU for GSI 

SMMU driver configures S1 protection by parsing
the GSI device node parameters.

Change-Id: Iafb17f5bde607a1f539daf7e2d1865153524ecce
parent d2b4d028

qcom/kona-qupv3.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -565,8 +565,8 @@ 
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		dmas = <&gpi_dma2 0 5 3 64 0>,

			<&gpi_dma2 1 5 3 64 0>;

		dmas = <&gpi_dma1 0 5 3 64 0>,

			<&gpi_dma1 1 5 3 64 0>;

		dma-names = "tx", "rx";

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_i2c_active>;

qcom/kona.dtsi

+7 −4
Original line number Diff line number Diff line
@@ -3470,12 +3470,13 @@ 
			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;

		qcom,max-num-gpii = <13>;

		qcom,max-num-gpii = <15>;

		qcom,gpii-mask = <0x7ff>;

		qcom,ev-factor = <2>;

		qcom,gpii_offset;

		iommus = <&apps_smmu 0x5b6 0x0>;

		qcom,smmu-cfg = <0x1>;

		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;

		status = "ok";

	};
@@ -3497,9 +3498,10 @@ 
		qcom,max-num-gpii = <10>;

		qcom,gpii-mask = <0x3f>;

		qcom,ev-factor = <2>;

		qcom,gpii_offset;

		iommus = <&apps_smmu 0x56 0x0>;

		qcom,smmu-cfg = <0x1>;

		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;

		status = "ok";

	};
@@ -3521,9 +3523,10 @@ 
		qcom,max-num-gpii = <10>;

		qcom,gpii-mask = <0x3f>;

		qcom,ev-factor = <2>;

		qcom,gpii_offset;

		iommus = <&apps_smmu 0x76 0x0>;

		qcom,smmu-cfg = <0x1>;

		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;

		status = "ok";

	};