Commit 282dc832 authored Oct 20, 2017 by Dave Airlie

drm-intel into drm-next

Last batch of drm/i915 features for v4.15:

- transparent huge pages support (Matthew)
- uapi: I915_PARAM_HAS_SCHEDULER into a capability bitmask (Chris)
- execlists: preemption (Chris)
- scheduler: user defined priorities (Chris)
- execlists optimization (Michał)
- plenty of display fixes (Imre)
- has_ipc fix (Rodrigo)
- platform features definition refactoring (Rodrigo)
- legacy cursor update fix (Maarten)
- fix vblank waits for cursor updates (Maarten)
- reprogram dmc firmware on resume, dmc state fix (Imre)
- remove use_mmio_flip module parameter (Maarten)
- wa fixes (Oscar)
- huc/guc firmware refacoring (Sagar, Michal)
- push encoder specific code to encoder hooks (Jani)
- DP MST fixes (Dhinakaran)
- eDP power sequencing fixes (Manasi)
- selftest updates (Chris, Matthew)
- mmu notifier cpu hotplug deadlock fix (Daniel)
- more VBT parser refactoring (Jani)
- max pipe refactoring (Mika Kahola)
- rc6/rps refactoring and separation (Sagar)
- userptr lockdep fix (Chris)
- tracepoint fixes and defunct tracepoint removal (Chris)
- use rcu instead of abusing stop_machine (Daniel)
- plenty of other fixes all around (Everyone)

* tag 'drm-intel-next-2017-10-12' of git://anongit.freedesktop.org/drm/drm-intel: (145 commits)
  drm/i915: Update DRIVER_DATE to 20171012
  drm/i915: Simplify intel_sanitize_enable_ppgtt
  drm/i915/userptr: Drop struct_mutex before cleanup
  drm/i915/dp: limit sink rates based on rate
  drm/i915/dp: centralize max source rate conditions more
  drm/i915: Allow PCH platforms fall back to BIOS LVDS mode
  drm/i915: Reuse normal state readout for LVDS/DVO fixed mode
  drm/i915: Use rcu instead of stop_machine in set_wedged
  drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup
  drm/i915: Create generic functions to control RC6, RPS
  drm/i915: Create generic function to setup LLC ring frequency table
  drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled
  drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "gt_pm"
  drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock
  drm/i915: Name i915_runtime_pm structure in dev_priv as "runtime_pm"
  drm/i915: Separate RPS and RC6 handling for CHV
  drm/i915: Separate RPS and RC6 handling for VLV
  drm/i915: Separate RPS and RC6 handling for BDW
  drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps
  drm/i915: Separate RPS and RC6 handling for gen6+
  ...

parents 6585d427 fa9caf0b

drivers/gpu/drm/i915/Makefile

+3 −0

Original line number	Diff line number	Diff line
		@@ -47,6 +47,7 @@ i915-y += i915_cmd_parser.o \
		i915_gem_tiling.o \
		i915_gem_timeline.o \
		i915_gem_userptr.o \
		i915_gemfs.o \
		i915_trace_points.o \
		i915_vma.o \
		intel_breadcrumbs.o \
		@@ -59,6 +60,8 @@ i915-y += i915_cmd_parser.o \

		# general-purpose microcontroller (GuC) support
		i915-y += intel_uc.o \
		intel_uc_fw.o \
		intel_guc.o \
		intel_guc_ct.o \
		intel_guc_log.o \
		intel_guc_loader.o \

drivers/gpu/drm/i915/gvt/scheduler.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -174,6 +174,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
		atomic_set(&workload->shadow_ctx_active, 1);
		break;
		case INTEL_CONTEXT_SCHEDULE_OUT:
		case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
		atomic_set(&workload->shadow_ctx_active, 0);
		break;
		default:

drivers/gpu/drm/i915/i915_debugfs.c

+146 −233

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drivers/gpu/drm/i915/i915_drv.c

+33 −15

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drivers/gpu/drm/i915/i915_drv.h

+64 −19

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