Loading drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c +4 −4 Original line number Diff line number Diff line Loading @@ -1419,7 +1419,7 @@ static int ipa_mpm_vote_unvote_pcie_clk(enum ipa_mpm_clk_vote_type vote, } mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); IPA_MPM_ERR("PCIe clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", IPA_MPM_DBG("PCIe clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", vote, probe_id, atomic_read(&ipa_mpm_ctx->md[probe_id].clk_cnt.pcie_clk_cnt)); Loading Loading @@ -1464,7 +1464,7 @@ static void ipa_mpm_vote_unvote_ipa_clk(enum ipa_mpm_clk_vote_type vote, if (vote > CLK_OFF) return; IPA_MPM_ERR("IPA clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", IPA_MPM_DBG("IPA clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", vote, probe_id, atomic_read(&ipa_mpm_ctx->md[probe_id].clk_cnt.ipa_clk_cnt)); Loading Loading @@ -1955,7 +1955,7 @@ static void ipa_mpm_read_channel(enum ipa_client_type chan) ep = &ipa3_ctx->ep[ipa_ep_idx]; IPA_MPM_ERR("Reading channel for chan %d, ep = %d, gsi_chan_hdl = %d\n", IPA_MPM_DBG("Reading channel for chan %d, ep = %d, gsi_chan_hdl = %d\n", chan, ep, ep->gsi_chan_hdl); res = ipa3_get_gsi_chan_info(&chan_info, ep->gsi_chan_hdl); Loading Loading @@ -2354,7 +2354,7 @@ static int ipa_mpm_mhi_probe_cb(struct mhi_device *mhi_dev, /* Check if ODL pipe is connected to MHIP DPL pipe before probe */ if (probe_id == IPA_MPM_MHIP_CH_ID_2 && ipa3_is_odl_connected()) { IPA_MPM_ERR("setting DPL DMA to ODL\n"); IPA_MPM_DBG("setting DPL DMA to ODL\n"); ret = ipa_mpm_set_dma_mode(IPA_CLIENT_MHI_PRIME_DPL_PROD, IPA_CLIENT_USB_DPL_CONS, false); } Loading Loading
drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c +4 −4 Original line number Diff line number Diff line Loading @@ -1419,7 +1419,7 @@ static int ipa_mpm_vote_unvote_pcie_clk(enum ipa_mpm_clk_vote_type vote, } mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); IPA_MPM_ERR("PCIe clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", IPA_MPM_DBG("PCIe clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", vote, probe_id, atomic_read(&ipa_mpm_ctx->md[probe_id].clk_cnt.pcie_clk_cnt)); Loading Loading @@ -1464,7 +1464,7 @@ static void ipa_mpm_vote_unvote_ipa_clk(enum ipa_mpm_clk_vote_type vote, if (vote > CLK_OFF) return; IPA_MPM_ERR("IPA clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", IPA_MPM_DBG("IPA clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", vote, probe_id, atomic_read(&ipa_mpm_ctx->md[probe_id].clk_cnt.ipa_clk_cnt)); Loading Loading @@ -1955,7 +1955,7 @@ static void ipa_mpm_read_channel(enum ipa_client_type chan) ep = &ipa3_ctx->ep[ipa_ep_idx]; IPA_MPM_ERR("Reading channel for chan %d, ep = %d, gsi_chan_hdl = %d\n", IPA_MPM_DBG("Reading channel for chan %d, ep = %d, gsi_chan_hdl = %d\n", chan, ep, ep->gsi_chan_hdl); res = ipa3_get_gsi_chan_info(&chan_info, ep->gsi_chan_hdl); Loading Loading @@ -2354,7 +2354,7 @@ static int ipa_mpm_mhi_probe_cb(struct mhi_device *mhi_dev, /* Check if ODL pipe is connected to MHIP DPL pipe before probe */ if (probe_id == IPA_MPM_MHIP_CH_ID_2 && ipa3_is_odl_connected()) { IPA_MPM_ERR("setting DPL DMA to ODL\n"); IPA_MPM_DBG("setting DPL DMA to ODL\n"); ret = ipa_mpm_set_dma_mode(IPA_CLIENT_MHI_PRIME_DPL_PROD, IPA_CLIENT_USB_DPL_CONS, false); } Loading