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Commit 2726e15e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.14' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

A few fixes for 4.14.  Nothing too major.

* 'drm-fixes-4.14' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: disable hard reset in hibernate for APUs
  drm/amdgpu: revert tile table update for oland
parents ffa34d85 82060854

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+188 −1
Original line number Diff line number Diff line
@@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 
				NUM_BANKS(ADDR_SURF_2_BANK);

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

	} else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) {

	} else if (adev->asic_type == CHIP_OLAND) {

		tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[8] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |

				NUM_BANKS(ADDR_SURF_8_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

	} else if (adev->asic_type == CHIP_HAINAN) {

		tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P2) |

drivers/gpu/drm/radeon/radeon_device.c

+1 −1
Original line number Diff line number Diff line
@@ -1663,7 +1663,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, 
	radeon_agp_suspend(rdev);



	pci_save_state(dev->pdev);

	if (freeze && rdev->family >= CHIP_CEDAR) {

	if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {

		rdev->asic->asic_reset(rdev, true);

		pci_restore_state(dev->pdev);

	} else if (suspend) {