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Commit 2699cdfb authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
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MIPS: Alchemy: move calc_clock function. 



Now that nothing in time.c depends on calc_clock, it can
be moved to clocks.c where it belongs.
While at it, give it a better non-generic name and call it
as soon as possible in plat_mem_init.

Signed-off-by: default avatarManuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 0c694de1

arch/mips/alchemy/common/clocks.c

+54 −0
Original line number Diff line number Diff line
@@ -27,11 +27,21 @@ 
 */



#include <linux/module.h>

#include <linux/spinlock.h>

#include <asm/time.h>

#include <asm/mach-au1x00/au1000.h>



/*

 * I haven't found anyone that doesn't use a 12 MHz source clock,

 * but just in case.....

 */

#define AU1000_SRC_CLK	12000000



static unsigned int au1x00_clock; /*  Hz */

static unsigned long uart_baud_base;



static DEFINE_SPINLOCK(time_lock);



/*

 * Set the au1000_clock

 */
@@ -60,3 +70,47 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) 
{

	uart_baud_base = new_baud_base;

}



/*

 * We read the real processor speed from the PLL.  This is important

 * because it is more accurate than computing it from the 32 KHz

 * counter, if it exists.  If we don't have an accurate processor

 * speed, all of the peripherals that derive their clocks based on

 * this advertised speed will introduce error and sometimes not work

 * properly.  This function is futher convoluted to still allow configurations

 * to do that in case they have really, really old silicon with a

 * write-only PLL register.			-- Dan

 */

unsigned long au1xxx_calc_clock(void)

{

	unsigned long cpu_speed;

	unsigned long flags;



	spin_lock_irqsave(&time_lock, flags);



	/*

	 * On early Au1000, sys_cpupll was write-only. Since these

	 * silicon versions of Au1000 are not sold by AMD, we don't bend

	 * over backwards trying to determine the frequency.

	 */

	if (au1xxx_cpu_has_pll_wo())

#ifdef CONFIG_SOC_AU1000_FREQUENCY

		cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;

#else

		cpu_speed = 396000000;

#endif

	else

		cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;



	/* On Alchemy CPU:counter ratio is 1:1 */

	mips_hpt_frequency = cpu_speed;

	/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */

	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)

							  & 0x03) + 2) * 16));



	spin_unlock_irqrestore(&time_lock, flags);



	set_au1x00_speed(cpu_speed);



	return cpu_speed;

}

arch/mips/alchemy/common/setup.c

+9 −0
Original line number Diff line number Diff line
@@ -44,6 +44,15 @@ extern void set_cpuspec(void); 


void __init plat_mem_setup(void)

{

	unsigned long est_freq;



	/* determine core clock */

	est_freq = au1xxx_calc_clock();

	est_freq += 5000;    /* round */

	est_freq -= est_freq % 10000;

	printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),

	       est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);



	_machine_restart = au1000_restart;

	_machine_halt = au1000_halt;

	pm_power_off = au1000_power_off;

arch/mips/alchemy/common/time.c

+0 −54
Original line number Diff line number Diff line
@@ -44,53 +44,6 @@ 


extern int allow_au1k_wait; /* default off for CP0 Counter */



static DEFINE_SPINLOCK(time_lock);



/*

 * I haven't found anyone that doesn't use a 12 MHz source clock,

 * but just in case.....

 */

#define AU1000_SRC_CLK	12000000



/*

 * We read the real processor speed from the PLL.  This is important

 * because it is more accurate than computing it from the 32 KHz

 * counter, if it exists.  If we don't have an accurate processor

 * speed, all of the peripherals that derive their clocks based on

 * this advertised speed will introduce error and sometimes not work

 * properly.  This function is futher convoluted to still allow configurations

 * to do that in case they have really, really old silicon with a

 * write-only PLL register.			-- Dan

 */

unsigned long calc_clock(void)

{

	unsigned long cpu_speed;

	unsigned long flags;



	spin_lock_irqsave(&time_lock, flags);



	/*

	 * On early Au1000, sys_cpupll was write-only. Since these

	 * silicon versions of Au1000 are not sold by AMD, we don't bend

	 * over backwards trying to determine the frequency.

	 */

	if (au1xxx_cpu_has_pll_wo())

#ifdef CONFIG_SOC_AU1000_FREQUENCY

		cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;

#else

		cpu_speed = 396000000;

#endif

	else

		cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;

	/* On Alchemy CPU:counter ratio is 1:1 */

	mips_hpt_frequency = cpu_speed;

	/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */

	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)

							  & 0x03) + 2) * 16));

	spin_unlock_irqrestore(&time_lock, flags);

	return cpu_speed;

}



static cycle_t au1x_counter1_read(void)

{

	return au_readl(SYS_RTCREAD);
@@ -150,13 +103,6 @@ void __init plat_time_init(void) 
{

	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;

	unsigned long t;

	unsigned int est_freq = calc_clock();



	est_freq += 5000;    /* round */

	est_freq -= est_freq%10000;

	printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(),

	       est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);

	set_au1x00_speed(est_freq);



	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock

	 * has been detected.  If so install the rtcmatch2 clocksource,

arch/mips/include/asm/mach-au1x00/au1000.h

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ extern void set_au1x00_speed(unsigned int new_freq); 
extern unsigned int get_au1x00_speed(void);

extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);

extern unsigned long get_au1x00_uart_baud_base(void);

extern unsigned long au1xxx_calc_clock(void);



/*

 * Every board describes its IRQ mapping with this table.