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Commit 2659d917 authored by Can Guo's avatar Can Guo
Browse files

phy: ufs: update Gear4 PHY settings for Kona 



Update UFS Gear4 PHY settings on Kona per new hardware programming guide.

Change-Id: I655fd5220c5d7a1fcbfea282c93df817ec446795
Signed-off-by: default avatarCan Guo <cang@codeaurora.org>
parent 2dcb751e

drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h

+22 −10
Original line number Diff line number Diff line
@@ -106,9 +106,11 @@ 
#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW		RX_OFF(0, 0x3C)

#define QSERDES_RX0_UCDR_PI_CTRL2			RX_OFF(0, 0x48)

#define QSERDES_RX0_RX_TERM_BW				RX_OFF(0, 0x80)

#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1		RX_OFF(0, 0xE8)

#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2		RX_OFF(0, 0xEC)

#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3		RX_OFF(0, 0xF0)

#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4		RX_OFF(0, 0xF4)

#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1		RX_OFF(0, 0x110)

#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2		RX_OFF(0, 0x114)

#define QSERDES_RX0_RX_IDAC_MEASURE_TIME		RX_OFF(0, 0x100)

#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW			RX_OFF(0, 0xF8)
@@ -129,6 +131,7 @@ 
#define QSERDES_RX0_RX_MODE_10_HIGH3			RX_OFF(0, 0x1A4)

#define QSERDES_RX0_RX_MODE_10_HIGH4			RX_OFF(0, 0x1A8)

#define QSERDES_RX0_DCC_CTRL1				RX_OFF(0, 0x1BC)

#define QSERDES_RX0_GM_CAL				RX_OFF(0, 0xDC)

#define QSERDES_RX0_AC_JTAG_ENABLE			RX_OFF(0, 0x68)

#define QSERDES_RX0_UCDR_FO_GAIN			RX_OFF(0, 0x08)

#define QSERDES_RX0_UCDR_SO_GAIN			RX_OFF(0, 0x14)
@@ -143,9 +146,11 @@ 
#define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW		RX_OFF(1, 0x3C)

#define QSERDES_RX1_UCDR_PI_CTRL2			RX_OFF(1, 0x48)

#define QSERDES_RX1_RX_TERM_BW				RX_OFF(1, 0x80)

#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1		RX_OFF(1, 0xE8)

#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2		RX_OFF(1, 0xEC)

#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3		RX_OFF(1, 0xF0)

#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4		RX_OFF(1, 0xF4)

#define QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1		RX_OFF(1, 0x110)

#define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2		RX_OFF(1, 0x114)

#define QSERDES_RX1_RX_IDAC_MEASURE_TIME		RX_OFF(1, 0x100)

#define QSERDES_RX1_RX_IDAC_TSETTLE_LOW			RX_OFF(1, 0xF8)
@@ -166,6 +171,7 @@ 
#define QSERDES_RX1_RX_MODE_10_HIGH3			RX_OFF(1, 0x1A4)

#define QSERDES_RX1_RX_MODE_10_HIGH4			RX_OFF(1, 0x1A8)

#define QSERDES_RX1_DCC_CTRL1				RX_OFF(1, 0x1BC)

#define QSERDES_RX1_GM_CAL				RX_OFF(1, 0xDC)

#define QSERDES_RX1_AC_JTAG_ENABLE			RX_OFF(1, 0x68)

#define QSERDES_RX1_UCDR_FO_GAIN			RX_OFF(1, 0x08)

#define QSERDES_RX1_UCDR_SO_GAIN			RX_OFF(1, 0x14)
@@ -214,7 +220,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x75),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0xE5),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
@@ -228,9 +234,11 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x6F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x09),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x20),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0x80),
@@ -239,7 +247,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x7F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x2C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0xE0),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0xC8),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xC8),
@@ -251,6 +259,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_GM_CAL, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
@@ -346,7 +355,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x75),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0xE5),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
@@ -360,9 +369,11 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x6F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x09),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x20),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0x80),
@@ -371,7 +382,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x7F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x2C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0xE0),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0xC8),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xC8),
@@ -383,6 +394,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_GM_CAL, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),

};