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Commit 2613885a authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Use correct log type for "Unused context label" message"

parents 16668cae be9af277

drivers/gpu/msm/a6xx_reg.h

+11 −0
Original line number Diff line number Diff line
@@ -1105,5 +1105,16 @@ 
#define A6XX_RGMU_CX_PCC_STATUS			0x1F83C

#define A6XX_RGMU_CX_PCC_DEBUG			0x1F83D



/* GPU CX_MISC registers */

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0	0x1

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1	0x2

#define A6XX_LLC_NUM_GPU_SCIDS			5

#define A6XX_GPU_LLC_SCID_NUM_BITS		5

#define A6XX_GPU_LLC_SCID_MASK \

	((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)

#define A6XX_GPUHTW_LLC_SCID_SHIFT		25

#define A6XX_GPUHTW_LLC_SCID_MASK \

	(((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)



#endif /* _A6XX_REG_H */

drivers/gpu/msm/adreno.c

+67 −0
Original line number Diff line number Diff line
@@ -1193,6 +1193,22 @@ static void adreno_cx_dbgc_probe(struct kgsl_device *device) 
		dev_warn(device->dev, "cx_dbgc ioremap failed\n");

}



static void adreno_cx_misc_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct resource *res;



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

					   "cx_misc");



	if (res == NULL)

		return;



	adreno_dev->cx_misc_len = resource_size(res);

	adreno_dev->cx_misc_virt = devm_ioremap(device->dev,

					res->start, adreno_dev->cx_misc_len);

}



static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev)

{

	unsigned int val;
@@ -1315,6 +1331,9 @@ static int adreno_probe(struct platform_device *pdev) 
	/* Probe for the optional CX_DBGC block */

	adreno_cx_dbgc_probe(device);



	/* Probe for the optional CX_MISC block */

	adreno_cx_misc_probe(device);



	/*

	 * qcom,iommu-secure-id is used to identify MMUs that can handle secure

	 * content but that is only part of the story - the GPU also has to be
@@ -3155,6 +3174,54 @@ void adreno_cx_dbgc_regwrite(struct kgsl_device *device, 
	__raw_writel(value, adreno_dev->cx_dbgc_virt + cx_dbgc_offset);

}



void adreno_cx_misc_regread(struct adreno_device *adreno_dev,

	unsigned int offsetwords, unsigned int *value)

{

	unsigned int cx_misc_offset;



	cx_misc_offset = (offsetwords << 2);

	if (!adreno_dev->cx_misc_virt ||

		(cx_misc_offset >= adreno_dev->cx_misc_len))

		return;



	*value = __raw_readl(adreno_dev->cx_misc_virt + cx_misc_offset);



	/*

	 * ensure this read finishes before the next one.

	 * i.e. act like normal readl()

	 */

	rmb();

}



void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev,

	unsigned int offsetwords, unsigned int value)

{

	unsigned int cx_misc_offset;



	cx_misc_offset = (offsetwords << 2);

	if (!adreno_dev->cx_misc_virt ||

		(cx_misc_offset >= adreno_dev->cx_misc_len))

		return;



	/*

	 * ensure previous writes post before this one,

	 * i.e. act like normal writel()

	 */

	wmb();

	__raw_writel(value, adreno_dev->cx_misc_virt + cx_misc_offset);

}



void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,

		unsigned int offsetwords,

		unsigned int mask, unsigned int bits)

{

	unsigned int val = 0;



	adreno_cx_misc_regread(adreno_dev, offsetwords, &val);

	val &= ~mask;

	adreno_cx_misc_regwrite(adreno_dev, offsetwords, val | bits);

}



/**

 * adreno_waittimestamp - sleep while waiting for the specified timestamp

 * @device - pointer to a KGSL device structure

drivers/gpu/msm/adreno.h

+13 −0
Original line number Diff line number Diff line
@@ -432,6 +432,8 @@ enum gpu_coresight_sources { 
 * @chipid: Chip ID specific to the GPU

 * @gmem_base: Base physical address of GMEM

 * @gmem_size: GMEM size

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @gpucore: Pointer to the adreno_gpu_core structure

 * @pfp_fw: Buffer which holds the pfp ucode

 * @pfp_fw_size: Size of pfp ucode buffer
@@ -512,6 +514,8 @@ struct adreno_device { 
	unsigned long cx_dbgc_base;

	unsigned int cx_dbgc_len;

	void __iomem *cx_dbgc_virt;

	unsigned int cx_misc_len;

	void __iomem *cx_misc_virt;

	const struct adreno_gpu_core *gpucore;

	struct adreno_firmware fw[2];

	size_t gpmu_cmds_size;
@@ -1164,6 +1168,14 @@ void adreno_cx_dbgc_regread(struct kgsl_device *adreno_device, 
		unsigned int offsetwords, unsigned int *value);

void adreno_cx_dbgc_regwrite(struct kgsl_device *device,

		unsigned int offsetwords, unsigned int value);

void adreno_cx_misc_regread(struct adreno_device *adreno_dev,

		unsigned int offsetwords, unsigned int *value);

void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev,

		unsigned int offsetwords, unsigned int value);

void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,

		unsigned int offsetwords,

		unsigned int mask, unsigned int bits);





#define ADRENO_TARGET(_name, _id) \

static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \
@@ -1280,6 +1292,7 @@ static inline int adreno_is_a6xx(struct adreno_device *adreno_dev) 
}



ADRENO_TARGET(a608, ADRENO_REV_A608)

ADRENO_TARGET(a618, ADRENO_REV_A618)

ADRENO_TARGET(a630, ADRENO_REV_A630)

ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a650, ADRENO_REV_A650)

drivers/gpu/msm/adreno_a6xx.c

+7 −48
Original line number Diff line number Diff line
@@ -24,18 +24,6 @@ 


#define MIN_HBB		13



#define A6XX_LLC_NUM_GPU_SCIDS		5

#define A6XX_GPU_LLC_SCID_NUM_BITS	5

#define A6XX_GPU_LLC_SCID_MASK \

	((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)

#define A6XX_GPUHTW_LLC_SCID_SHIFT	25

#define A6XX_GPUHTW_LLC_SCID_MASK \

	(((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)



#define A6XX_GPU_CX_REG_BASE		0x509E000

#define A6XX_GPU_CX_REG_SIZE		0x1000





static const struct adreno_vbif_data a630_vbif[] = {

	{A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009},

	{A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3},
@@ -1646,24 +1634,6 @@ static void a6xx_err_callback(struct adreno_device *adreno_dev, int bit) 
	}

}



/* GPU System Cache control registers */

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0   0x4

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1   0x8



static inline void _reg_rmw(void __iomem *regaddr,

	unsigned int mask, unsigned int bits)

{

	unsigned int val = 0;



	val = __raw_readl(regaddr);

	/* Make sure the above read completes before we proceed  */

	rmb();

	val &= ~mask;

	__raw_writel(val | bits, regaddr);

	/* Make sure the above write posts before we proceed*/

	wmb();

}



/*

 * a6xx_llc_configure_gpu_scid() - Program the sub-cache ID for all GPU blocks

 * @adreno_dev: The adreno device pointer
@@ -1683,13 +1653,9 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,

			A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

	} else {

		void __iomem *gpu_cx_reg;



		gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE,

			A6XX_GPU_CX_REG_SIZE);

		_reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

		adreno_cx_misc_regrmw(adreno_dev,

				A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

				A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

		iounmap(gpu_cx_reg);

	}

}
@@ -1700,7 +1666,6 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev)

{

	uint32_t gpuhtw_scid;

	void __iomem *gpu_cx_reg;



	/*

	 * On A640, the GPUHTW SCID is configured via a NoC override in the
@@ -1711,11 +1676,10 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) 


	gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);



	gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE);

	_reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

	adreno_cx_misc_regrmw(adreno_dev,

			A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

			A6XX_GPUHTW_LLC_SCID_MASK,

			gpuhtw_scid << A6XX_GPUHTW_LLC_SCID_SHIFT);

	iounmap(gpu_cx_reg);

}



/*
@@ -1724,8 +1688,6 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) 
 */

static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev)

{

	void __iomem *gpu_cx_reg;



	/*

	 * Attributes override through GBIF is not supported with MMU-500.

	 * Attributes are used as configured through SMMU pagetable entries.
@@ -1739,11 +1701,8 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) 
	 *      writenoallocoverrideen=1

	 *      write-no-alloc=1 - Do not allocates lines on write miss

	 */

	gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE);

	__raw_writel(0x3, gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0);

	/* Make sure the above write posts before we proceed*/

	wmb();

	iounmap(gpu_cx_reg);

	adreno_cx_misc_regwrite(adreno_dev,

			A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0, 0x3);

}



static const char *fault_block[8] = {

drivers/gpu/msm/adreno_a6xx_gmu.c

+2 −2
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device) 
	_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0);

	_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);



	if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev))

	if ((ADRENO_GPUREV(adreno_dev) >= 640) || adreno_is_a618(adreno_dev))

		_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,

				0x30090);

	else
@@ -206,7 +206,7 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device) 
	_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3);

	_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);



	if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev))

	if ((ADRENO_GPUREV(adreno_dev) >= 640) || adreno_is_a618(adreno_dev))

		_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2,

				0x30090);

	else