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Commit 2602087e authored by Christoffer Dall's avatar Christoffer Dall
Browse files

KVM: arm/arm64: Allow GICv2 to supply a uaccess register function 



We are about to differentiate between writes from a VCPU and from
userspace to the GIC's GICD_ISACTIVER and GICD_ICACTIVER registers due
to different synchronization requirements.

Expand the macro to define a register description for the GIC to take
uaccess functions as well.

Signed-off-by: default avatarChristoffer Dall <cdall@linaro.org>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent e8ec032b

virt/kvm/arm/vgic/vgic-mmio-v2.c

+11 −11
Original line number Diff line number Diff line
@@ -296,34 +296,34 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { 
		vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,

		vgic_mmio_read_rao, vgic_mmio_write_wi, 1,

		vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,

		vgic_mmio_read_enable, vgic_mmio_write_senable, 1,

		vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,

		vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,

		vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,

		vgic_mmio_read_pending, vgic_mmio_write_spending, 1,

		vgic_mmio_read_pending, vgic_mmio_write_spending, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,

		vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,

		vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,

		vgic_mmio_read_active, vgic_mmio_write_sactive, 1,

		vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,

		vgic_mmio_read_active, vgic_mmio_write_cactive, 1,

		vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,

		vgic_mmio_read_priority, vgic_mmio_write_priority, 8,

		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),

		vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,

		8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,

		vgic_mmio_read_target, vgic_mmio_write_target, 8,

		vgic_mmio_read_target, vgic_mmio_write_target, NULL, NULL, 8,

		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,

		vgic_mmio_read_config, vgic_mmio_write_config, 2,

		vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,

		vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,

virt/kvm/arm/vgic/vgic-mmio.h

+3 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ extern struct kvm_io_device_ops kvm_io_gic_ops; 
 * The _WITH_LENGTH version instantiates registers with a fixed length

 * and is mutually exclusive with the _PER_IRQ version.

 */

#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc)		\

#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, ur, uw, bpi, acc)	\

	{								\

		.reg_offset = off,					\

		.bits_per_irq = bpi,					\
@@ -83,6 +83,8 @@ extern struct kvm_io_device_ops kvm_io_gic_ops; 
		.access_flags = acc,					\

		.read = rd,						\

		.write = wr,						\

		.uaccess_read = ur,					\

		.uaccess_write = uw,					\

	}



#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc)		\