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Commit 25f480e8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2017-05-29' of... 

Merge tag 'drm-intel-fixes-2017-05-29' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes

drm/i915 fixes for v4.12-rc4

* tag 'drm-intel-fixes-2017-05-29' of git://anongit.freedesktop.org/git/drm-intel:
  drm/i915: Stop pretending to mask/unmask LPE audio interrupts
  drm/i915/selftests: Silence compiler warning in igt_ctx_exec
  Revert "drm/i915: Restore lost "Initialized i915" welcome message"
  drm/i915/gvt: clean up unsubmited workloads before destroying kmem cache
  drm/i915/gvt: Disable compression workaround for Gen9
  drm/i915: set initialised only when init_context callback is NULL
  drm/i915: Fix new -Wint-in-bool-context gcc compiler warning
  drm/i915: use vma->size for appgtt allocate_va_range
  drm/i915: Do not sync RCU during shrinking
parents 5ed02dbb 9bd95909

drivers/gpu/drm/i915/gvt/execlist.c

+20 −10
Original line number Diff line number Diff line
@@ -779,8 +779,26 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id) 
	vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

}



static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_engine_cs *engine;

	struct intel_vgpu_workload *pos, *n;

	unsigned int tmp;



	/* free the unsubmited workloads in the queues. */

	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {

		list_for_each_entry_safe(pos, n,

			&vgpu->workload_q_head[engine->id], list) {

			list_del_init(&pos->list);

			free_workload(pos);

		}

	}

}



void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu)

{

	clean_workloads(vgpu, ALL_ENGINES);

	kmem_cache_destroy(vgpu->workloads);

}
@@ -811,17 +829,9 @@ void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu, 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_engine_cs *engine;

	struct intel_vgpu_workload *pos, *n;

	unsigned int tmp;



	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {

		/* free the unsubmited workload in the queue */

		list_for_each_entry_safe(pos, n,

			&vgpu->workload_q_head[engine->id], list) {

			list_del_init(&pos->list);

			free_workload(pos);

		}



	clean_workloads(vgpu, engine_mask);

	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)

		init_vgpu_execlist(vgpu, engine->id);

}
 
}

drivers/gpu/drm/i915/gvt/handlers.c

+21 −9
Original line number Diff line number Diff line
@@ -1366,18 +1366,28 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 
		void *p_data, unsigned int bytes)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	i915_reg_t reg = {.reg = offset};

	u32 v = *(u32 *)p_data;



	if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))

		return intel_vgpu_default_mmio_write(vgpu,

				offset, p_data, bytes);



	switch (offset) {

	case 0x4ddc:

		vgpu_vreg(vgpu, offset) = 0x8000003c;

		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */

		I915_WRITE(reg, vgpu_vreg(vgpu, offset));

		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */

		vgpu_vreg(vgpu, offset) = v & ~(1 << 31);

		break;

	case 0x42080:

		vgpu_vreg(vgpu, offset) = 0x8000;

		/* WaCompressedResourceDisplayNewHashMode:skl */

		I915_WRITE(reg, vgpu_vreg(vgpu, offset));

		/* bypass WaCompressedResourceDisplayNewHashMode */

		vgpu_vreg(vgpu, offset) = v & ~(1 << 15);

		break;

	case 0xe194:

		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */

		vgpu_vreg(vgpu, offset) = v & ~(1 << 8);

		break;

	case 0x7014:

		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */

		vgpu_vreg(vgpu, offset) = v & ~(1 << 13);

		break;

	default:

		return -EINVAL;
@@ -1634,7 +1644,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

		NULL, NULL);

	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,

		 skl_misc_ctl_write);

	MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
@@ -2568,7 +2579,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(0x6e570, D_BDW_PLUS);

	MMIO_D(0x65f10, D_BDW_PLUS);



	MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,

		 skl_misc_ctl_write);

	MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/i915_drv.c

+0 −4
Original line number Diff line number Diff line
@@ -1272,10 +1272,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) 


	dev_priv->ipc_enabled = false;



	/* Everything is in place, we can now relax! */

	DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",

		 driver.name, driver.major, driver.minor, driver.patchlevel,

		 driver.date, pci_name(pdev), dev_priv->drm.primary->index);

	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))

		DRM_INFO("DRM_I915_DEBUG enabled\n");

	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))

drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -2313,7 +2313,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, 
		    appgtt->base.allocate_va_range) {

			ret = appgtt->base.allocate_va_range(&appgtt->base,

							     vma->node.start,

							     vma->node.size);

							     vma->size);

			if (ret)

				goto err_pages;

		}

drivers/gpu/drm/i915/i915_gem_shrinker.c

+0 −5
Original line number Diff line number Diff line
@@ -59,9 +59,6 @@ static void i915_gem_shrinker_unlock(struct drm_device *dev, bool unlock) 
		return;



	mutex_unlock(&dev->struct_mutex);



	/* expedite the RCU grace period to free some request slabs */

	synchronize_rcu_expedited();

}



static bool any_vma_pinned(struct drm_i915_gem_object *obj)
@@ -274,8 +271,6 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv) 
				I915_SHRINK_ACTIVE);

	intel_runtime_pm_put(dev_priv);



	synchronize_rcu(); /* wait for our earlier RCU delayed slab frees */



	return freed;

}