Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25c3d67e authored by Yujun Zhang's avatar Yujun Zhang
Browse files

ARM: dts: msm: add dynamic clock switch support on lito 

Enable dynamic clock switch feature for sw43404 amoled panel on
lito.

Change-Id: I66582ceecf0d789d50bf9d57cee974ef7011d049
parent 24dab89f

qcom/lito-sde-display.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -203,6 +203,10 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;



	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>;



	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";
@@ -230,6 +234,11 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;



	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list =

		<534712320 532484352 530256384>;



	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";
@@ -485,6 +494,15 @@ 


&dsi_nt35695b_truly_fhd_cmd {

	qcom,ulps-enabled;



	qcom,dsi-ctrl-num = <0>;

	qcom,dsi-phy-num = <0>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";



	qcom,dsi-sec-ctrl-num = <1>;

	qcom,dsi-sec-phy-num = <1>;

	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";



	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
@@ -505,6 +523,15 @@ 


&dsi_nt35695b_truly_fhd_video {

	qcom,esd-check-enabled;



	qcom,dsi-ctrl-num = <0>;

	qcom,dsi-phy-num = <0>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";



	qcom,dsi-sec-ctrl-num = <1>;

	qcom,dsi-sec-phy-num = <1>;

	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";



	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

qcom/lito-sde-pll.dtsi

+9 −4
Original line number Diff line number Diff line
@@ -6,11 +6,14 @@ 
		#clock-cells = <1>;

		reg = <0xae94900 0x280>,

		      <0xae94400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		      <0xaf03000 0x8>,

		      <0xae94200 0x100>;

		reg-names = "pll_base", "phy_base", "gdsc_base",

				"dynamic_pll_base";

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		memory-region = <&dfps_data_memory>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";
@@ -35,8 +38,10 @@ 
		#clock-cells = <1>;

		reg = <0xae96900 0x280>,

		      <0xae96400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		      <0xaf03000 0x8>,

		      <0xae96200 0x100>;

		reg-names = "pll_base", "phy_base", "gdsc_base",

				"dynamic_pll_base";

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

qcom/lito-sde.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -592,8 +592,9 @@ 
		compatible = "qcom,dsi-phy-v4.1";

		label = "dsi-phy-0";

		cell-index = <0>;

		reg = <0xae94400 0x800>;

		reg-names = "dsi_phy";

		reg = <0xae94400 0x800>,

			<0xae94200 0x100>;

		reg-names = "dsi_phy", "dyn_refresh_base";

		vdda-0p9-supply = <&L5A>;

		qcom,platform-strength-ctrl = [55 03

						55 03
@@ -624,8 +625,9 @@ 
		compatible = "qcom,dsi-phy-v4.1";

		label = "dsi-phy-1";

		cell-index = <1>;

		reg = <0xae96400 0x800>;

		reg-names = "dsi_phy";

		reg = <0xae96400 0x800>,

			<0xae96200 0x100>;

		reg-names = "dsi_phy", "dyn_refresh_base";

		vdda-0p9-supply = <&L5A>;

		qcom,platform-strength-ctrl = [55 03

						55 03

qcom/lito.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -579,10 +579,15 @@ 
		};



		cont_splash_memory: cont_splash_region {

			reg = <0x0 0xA0000000 0x0 0x02400000>;

			reg = <0x0 0xA0000000 0x0 0x02300000>;

			label = "cont_splash_region";

		};



		dfps_data_memory: dfps_data_region@a2300000 {

			reg = <0x0 0xa2300000 0x0 0x0100000>;

			label = "dfps_data_region";

		};



		dump_mem: mem_dump_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;