Loading arch/arm/mach-exynos/common.h +0 −1 Original line number Original line Diff line number Diff line Loading @@ -55,7 +55,6 @@ enum sys_powerdown { NUM_SYS_POWERDOWN, NUM_SYS_POWERDOWN, }; }; extern unsigned long l2x0_regs_phys; struct exynos_pmu_conf { struct exynos_pmu_conf { void __iomem *reg; void __iomem *reg; unsigned int val[NUM_SYS_POWERDOWN]; unsigned int val[NUM_SYS_POWERDOWN]; Loading arch/arm/mach-exynos/exynos.c +1 −11 Original line number Original line Diff line number Diff line Loading @@ -318,17 +318,7 @@ core_initcall(exynos_core_init); static int __init exynos4_l2x0_cache_init(void) static int __init exynos4_l2x0_cache_init(void) { { int ret; return l2x0_of_init(0x3c400001, 0xc20fffff); ret = l2x0_of_init(0x3c400001, 0xc20fffff); if (ret) return ret; if (IS_ENABLED(CONFIG_S5P_SLEEP)) { l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); } return 0; } } early_initcall(exynos4_l2x0_cache_init); early_initcall(exynos4_l2x0_cache_init); Loading arch/arm/mach-exynos/sleep.S +1 −29 Original line number Original line Diff line number Diff line Loading @@ -16,8 +16,6 @@ */ */ #include <linux/linkage.h> #include <linux/linkage.h> #include <asm/asm-offsets.h> #include <asm/hardware/cache-l2x0.h> #define CPU_MASK 0xff0ffff0 #define CPU_MASK 0xff0ffff0 #define CPU_CORTEX_A9 0x410fc090 #define CPU_CORTEX_A9 0x410fc090 Loading Loading @@ -53,33 +51,7 @@ ENTRY(exynos_cpu_resume) and r0, r0, r1 and r0, r0, r1 ldr r1, =CPU_CORTEX_A9 ldr r1, =CPU_CORTEX_A9 cmp r0, r1 cmp r0, r1 bne skip_l2_resume bleq l2c310_early_resume adr r0, l2x0_regs_phys ldr r0, [r0] cmp r0, #0 beq skip_l2_resume ldr r1, [r0, #L2X0_R_PHY_BASE] ldr r2, [r1, #L2X0_CTRL] tst r2, #0x1 bne skip_l2_resume ldr r2, [r0, #L2X0_R_AUX_CTRL] str r2, [r1, #L2X0_AUX_CTRL] ldr r2, [r0, #L2X0_R_TAG_LATENCY] str r2, [r1, #L310_TAG_LATENCY_CTRL] ldr r2, [r0, #L2X0_R_DATA_LATENCY] str r2, [r1, #L310_DATA_LATENCY_CTRL] ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] str r2, [r1, #L310_PREFETCH_CTRL] ldr r2, [r0, #L2X0_R_PWR_CTRL] str r2, [r1, #L310_POWER_CTRL] mov r2, #1 str r2, [r1, #L2X0_CTRL] skip_l2_resume: #endif #endif b cpu_resume b cpu_resume ENDPROC(exynos_cpu_resume) ENDPROC(exynos_cpu_resume) #ifdef CONFIG_CACHE_L2X0 .globl l2x0_regs_phys l2x0_regs_phys: .long 0 #endif arch/arm/plat-samsung/s5p-sleep.S +0 −1 Original line number Original line Diff line number Diff line Loading @@ -22,7 +22,6 @@ */ */ #include <linux/linkage.h> #include <linux/linkage.h> #include <asm/asm-offsets.h> .data .data .align .align Loading Loading
arch/arm/mach-exynos/common.h +0 −1 Original line number Original line Diff line number Diff line Loading @@ -55,7 +55,6 @@ enum sys_powerdown { NUM_SYS_POWERDOWN, NUM_SYS_POWERDOWN, }; }; extern unsigned long l2x0_regs_phys; struct exynos_pmu_conf { struct exynos_pmu_conf { void __iomem *reg; void __iomem *reg; unsigned int val[NUM_SYS_POWERDOWN]; unsigned int val[NUM_SYS_POWERDOWN]; Loading
arch/arm/mach-exynos/exynos.c +1 −11 Original line number Original line Diff line number Diff line Loading @@ -318,17 +318,7 @@ core_initcall(exynos_core_init); static int __init exynos4_l2x0_cache_init(void) static int __init exynos4_l2x0_cache_init(void) { { int ret; return l2x0_of_init(0x3c400001, 0xc20fffff); ret = l2x0_of_init(0x3c400001, 0xc20fffff); if (ret) return ret; if (IS_ENABLED(CONFIG_S5P_SLEEP)) { l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); } return 0; } } early_initcall(exynos4_l2x0_cache_init); early_initcall(exynos4_l2x0_cache_init); Loading
arch/arm/mach-exynos/sleep.S +1 −29 Original line number Original line Diff line number Diff line Loading @@ -16,8 +16,6 @@ */ */ #include <linux/linkage.h> #include <linux/linkage.h> #include <asm/asm-offsets.h> #include <asm/hardware/cache-l2x0.h> #define CPU_MASK 0xff0ffff0 #define CPU_MASK 0xff0ffff0 #define CPU_CORTEX_A9 0x410fc090 #define CPU_CORTEX_A9 0x410fc090 Loading Loading @@ -53,33 +51,7 @@ ENTRY(exynos_cpu_resume) and r0, r0, r1 and r0, r0, r1 ldr r1, =CPU_CORTEX_A9 ldr r1, =CPU_CORTEX_A9 cmp r0, r1 cmp r0, r1 bne skip_l2_resume bleq l2c310_early_resume adr r0, l2x0_regs_phys ldr r0, [r0] cmp r0, #0 beq skip_l2_resume ldr r1, [r0, #L2X0_R_PHY_BASE] ldr r2, [r1, #L2X0_CTRL] tst r2, #0x1 bne skip_l2_resume ldr r2, [r0, #L2X0_R_AUX_CTRL] str r2, [r1, #L2X0_AUX_CTRL] ldr r2, [r0, #L2X0_R_TAG_LATENCY] str r2, [r1, #L310_TAG_LATENCY_CTRL] ldr r2, [r0, #L2X0_R_DATA_LATENCY] str r2, [r1, #L310_DATA_LATENCY_CTRL] ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] str r2, [r1, #L310_PREFETCH_CTRL] ldr r2, [r0, #L2X0_R_PWR_CTRL] str r2, [r1, #L310_POWER_CTRL] mov r2, #1 str r2, [r1, #L2X0_CTRL] skip_l2_resume: #endif #endif b cpu_resume b cpu_resume ENDPROC(exynos_cpu_resume) ENDPROC(exynos_cpu_resume) #ifdef CONFIG_CACHE_L2X0 .globl l2x0_regs_phys l2x0_regs_phys: .long 0 #endif
arch/arm/plat-samsung/s5p-sleep.S +0 −1 Original line number Original line Diff line number Diff line Loading @@ -22,7 +22,6 @@ */ */ #include <linux/linkage.h> #include <linux/linkage.h> #include <asm/asm-offsets.h> .data .data .align .align Loading