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Commit 25a64025 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/sec: namespace + nvidia gpu names (no binary change) 



The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 4d34686e

drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h

+2 −1
Original line number Diff line number Diff line 
#ifndef __NVKM_SEC_H__

#define __NVKM_SEC_H__

extern struct nouveau_oclass nv98_sec_oclass;

#include <core/engine.h>

extern struct nvkm_oclass g98_sec_oclass;

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

+3 −3
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;

		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
@@ -313,7 +313,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;

		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
@@ -342,7 +342,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;

		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild

+1 −1
Original line number Diff line number Diff line 
nvkm-y += nvkm/engine/sec/nv98.o
 
nvkm-y += nvkm/engine/sec/g98.o

drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s→drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s

+3 −3
Original line number Diff line number Diff line 
/*

 *  fuc microcode for nv98 psec engine

 *  fuc microcode for g98 psec engine

 *  Copyright (C) 2010  Marcin Kościelnicki

 *

 *  This program is free software; you can redistribute it and/or modify
@@ -17,7 +17,7 @@ 
 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



.section #nv98_psec_data

.section #g98_psec_data



ctx_dma:

ctx_dma_query:		.b32 0
@@ -94,7 +94,7 @@ sec_dtable: 


.align 0x100



.section #nv98_psec_code

.section #g98_psec_code



	// $r0 is always set to 0 in our code - this allows some space savings.

	clear b32 $r0

drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h→drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h

+2 −2
Original line number Diff line number Diff line 
uint32_t nv98_psec_data[] = {

uint32_t g98_psec_data[] = {

/* 0x0000: ctx_dma */

/* 0x0000: ctx_dma_query */

	0x00000000,
@@ -150,7 +150,7 @@ uint32_t nv98_psec_data[] = { 
	0x00000000,

};



uint32_t nv98_psec_code[] = {

uint32_t g98_psec_code[] = {

	0x17f004bd,

	0x0010fe35,

	0xf10004fe,