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Commit 2543833e authored by Neeraj Soni's avatar Neeraj Soni Committed by Blagovest Kolenichev
Browse files

mmc: cqhci: Add inline crypto support to cqhci 



Wire up cqhci.c with the eMMC Crypto API and support for block layer inline
encryption additions and the keyslot manager.

Change-Id: I6860cd29d6f044f559385d438048b850faf9a8be
Signed-off-by: default avatarNeeraj Soni <neersoni@codeaurora.org>
parent 32f1d1ca

drivers/mmc/host/cqhci.c

+73 −1
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 


#include "../core/queue.h"

#include "cqhci.h"

#include "cqhci-crypto.h"



#include "sdhci-msm.h"



#define DCMD_SLOT 31
@@ -155,6 +157,8 @@ static void cqhci_dumpregs(struct cqhci_host *cq_host) 
	CQHCI_DUMP("Vendor cfg 0x%08x\n",

		   cqhci_readl(cq_host, CQHCI_VENDOR_CFG + offset));



	cqhci_crypto_debug(cq_host);



	if (cq_host->ops->dumpregs)

		cq_host->ops->dumpregs(mmc);

	else
@@ -275,6 +279,11 @@ static void __cqhci_enable(struct cqhci_host *cq_host) 
	if (cq_host->caps & CQHCI_TASK_DESC_SZ_128)

		cqcfg |= CQHCI_TASK_DESC_SZ;



	if (cqhci_host_is_crypto_supported(cq_host)) {

		cqhci_crypto_enable(cq_host);

		cqcfg |= CQHCI_ICE_ENABLE;

	}



	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);



	cqcfg |= CQHCI_ENABLE;
@@ -310,6 +319,9 @@ static void __cqhci_disable(struct cqhci_host *cq_host) 
{

	u32 cqcfg;



	if (cqhci_host_is_crypto_supported(cq_host))

		cqhci_crypto_disable(cq_host);



	cqcfg = cqhci_readl(cq_host, CQHCI_CFG);

	cqcfg &= ~CQHCI_ENABLE;

	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
@@ -317,6 +329,7 @@ static void __cqhci_disable(struct cqhci_host *cq_host) 
	cq_host->mmc->cqe_on = false;



	cq_host->activated = false;



	mmc_log_string(cq_host->mmc, "CQ disabled\n");

}
@@ -324,6 +337,8 @@ int cqhci_suspend(struct mmc_host *mmc) 
{

	struct cqhci_host *cq_host = mmc->cqe_private;



	cqhci_crypto_suspend(cq_host);



	if (cq_host->enabled)

		__cqhci_disable(cq_host);
@@ -608,6 +623,30 @@ static inline int cqhci_tag(struct mmc_request *mrq) 
	return mrq->cmd ? DCMD_SLOT : mrq->tag;

}



static inline

void cqhci_prep_crypto_desc(struct cqhci_host *cq_host, u64 *task_desc,

			u64 ice_ctx)

{

	u64 *ice_desc = NULL;



	if (cq_host->caps & CQHCI_CAP_CRYPTO_SUPPORT) {

		/*

		 * Get the address of ice context for the given task descriptor.

		 * ice context is present in the upper 64bits of task descriptor

		 * ice_conext_base_address = task_desc + 8-bytes

		 */

		ice_desc = (u64 *)((u8 *)task_desc +

					CQHCI_TASK_DESC_ICE_PARAM_OFFSET);

		memset(ice_desc, 0, CQHCI_TASK_DESC_ICE_PARAMS_SIZE);



		/*

		 *  Assign upper 64bits data of task descritor with ice context

		 */

		if (ice_ctx)

			*ice_desc = cpu_to_le64(ice_ctx);

	}

}



static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)

{

	int err = 0;
@@ -617,6 +656,7 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 
	struct cqhci_host *cq_host = mmc->cqe_private;

	unsigned long flags;

	struct sdhci_host *host = mmc_priv(mmc);

	u64 ice_ctx = 0;



	if (!cq_host->enabled) {

		pr_err("%s: cqhci: not enabled\n", mmc_hostname(mmc));
@@ -641,9 +681,17 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 
	}



	if (mrq->data) {

		err = cqhci_crypto_get_ctx(cq_host, mrq, &ice_ctx);

		if (err) {

			mmc->err_stats[MMC_ERR_ICE_CFG]++;

			pr_err("%s: failed to retrieve crypto ctx for tag %d\n",

				mmc_hostname(mmc), tag);

			goto out;

		}

		task_desc = (__le64 __force *)get_desc(cq_host, tag);

		cqhci_prep_task_desc(mrq, &data, 1);

		*task_desc = cpu_to_le64(data);

		cqhci_prep_crypto_desc(cq_host, task_desc, ice_ctx);



		err = cqhci_prep_tran_desc(mrq, cq_host, tag);

		if (err) {
@@ -690,6 +738,9 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 


	if (err)

		cqhci_post_req(mmc, mrq);



	if (mrq->data)

		cqhci_complete_crypto_desc(cq_host, mrq, NULL);

out:

	return err;

}
@@ -697,7 +748,15 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 
static void cqhci_crypto_update_queue(struct mmc_host *mmc,

					struct request_queue *queue)

{

	//struct cqhci_host *cq_host = mmc->cqe_private;

	struct cqhci_host *cq_host = mmc->cqe_private;



	if (cq_host->caps & CQHCI_CAP_CRYPTO_SUPPORT) {

		if (queue)

			cqhci_crypto_setup_rq_keyslot_manager(cq_host, queue);

		else

			pr_err("%s can not register keyslot manager\n",

				mmc_hostname(mmc));

	}

}



static void cqhci_recovery_needed(struct mmc_host *mmc, struct mmc_request *mrq,
@@ -821,6 +880,8 @@ static void cqhci_finish_mrq(struct mmc_host *mmc, unsigned int tag) 


	data = mrq->data;

	if (data) {

		cqhci_complete_crypto_desc(cq_host, mrq, NULL);



		if (data->error)

			data->bytes_xfered = 0;

		else
@@ -1028,6 +1089,8 @@ static void cqhci_recovery_start(struct mmc_host *mmc) 


	pr_debug("%s: cqhci: %s\n", mmc_hostname(mmc), __func__);



	cqhci_crypto_reset(cq_host);



	WARN_ON(!cq_host->recovery_halt);



	cqhci_halt(mmc, CQHCI_START_HALT_TIMEOUT);
@@ -1148,6 +1211,8 @@ static void cqhci_recovery_finish(struct mmc_host *mmc) 


	cqhci_set_irqs(cq_host, CQHCI_IS_MASK);



	cqhci_crypto_recovery_finish(cq_host);



	pr_debug("%s: cqhci: recovery done\n", mmc_hostname(mmc));

	mmc_log_string(mmc, "recovery done\n");

}
@@ -1236,6 +1301,13 @@ int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, 


	spin_lock_init(&cq_host->lock);



	err = cqhci_host_init_crypto(cq_host);

	if (err) {

		pr_err("%s: CQHCI version %u.%02u Crypto init failed err %d\n",

		       mmc_hostname(mmc), cqhci_ver_major(cq_host),

		       cqhci_ver_minor(cq_host), err);

	}



	init_completion(&cq_host->halt_comp);

	init_waitqueue_head(&cq_host->wait_queue);

drivers/mmc/host/cqhci.h

+22 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
#define CQHCI_DCMD			0x00001000

#define CQHCI_TASK_DESC_SZ		0x00000100

#define CQHCI_ENABLE			0x00000001

#define CQHCI_ICE_ENABLE		0x00000002



/* control */

#define CQHCI_CTL			0x0C
@@ -167,10 +168,19 @@ 
#define CQHCI_DAT_LENGTH(x)		(((x) & 0xFFFF) << 16)

#define CQHCI_DAT_ADDR_LO(x)		(((x) & 0xFFFFFFFF) << 32)

#define CQHCI_DAT_ADDR_HI(x)		(((x) & 0xFFFFFFFF) << 0)

#define DATA_UNIT_NUM(x)		(((u64)(x) & 0xFFFFFFFF) << 0)

#define CRYPTO_CONFIG_INDEX(x)		(((u64)(x) & 0xFF) << 32)

#define CRYPTO_ENABLE(x)		(((u64)(x) & 0x1) << 47)



/* ICE context is present in the upper 64bits of task descriptor */

#define CQHCI_TASK_DESC_ICE_PARAM_OFFSET	8

/* ICE descriptor size */

#define CQHCI_TASK_DESC_ICE_PARAMS_SIZE		8



struct cqhci_host_ops;

struct mmc_host;

struct cqhci_slot;

struct cqhci_host;



/* CCAP - Crypto Capability 100h */

union cqhci_crypto_capabilities {
@@ -258,6 +268,7 @@ struct cqhci_host_crypto_variant_ops { 
struct cqhci_host {

	const struct cqhci_host_ops *ops;

	void __iomem *mmio;

	void __iomem *icemmio;

	struct mmc_host *mmc;



	spinlock_t lock;
@@ -273,6 +284,7 @@ struct cqhci_host { 
	u32 dcmd_slot;

	u32 caps;

#define CQHCI_TASK_DESC_SZ_128		0x1

#define CQHCI_CAP_CRYPTO_SUPPORT	0x2



	u32 quirks;

#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ	0x1
@@ -309,6 +321,16 @@ struct cqhci_host { 
	struct completion halt_comp;

	wait_queue_head_t wait_queue;

	struct cqhci_slot *slot;

	const struct cqhci_host_crypto_variant_ops *crypto_vops;



#ifdef CONFIG_MMC_CQHCI_CRYPTO

	union cqhci_crypto_capabilities crypto_capabilities;

	union cqhci_crypto_cap_entry *crypto_cap_array;

	u32 crypto_cfg_register;

#ifdef CONFIG_BLK_INLINE_ENCRYPTION

	struct keyslot_manager *ksm;

#endif /* CONFIG_BLK_INLINE_ENCRYPTION */

#endif /* CONFIG_SCSI_CQHCI_CRYPTO */

};



struct cqhci_host_ops {