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Commit 24d46399 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm/drm/sde: update _setup_dspp_ops for CCN check"

parents bb9f2775 39b3955f

drivers/gpu/drm/msm/sde/sde_color_processing.c

+8 −0
Original line number Diff line number Diff line
@@ -643,10 +643,18 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, 
	int ret = 0;

	struct sde_ad_hw_cfg ad_cfg;



	memset(&hw_cfg, 0, sizeof(hw_cfg));

	sde_cp_get_hw_payload(prop_node, &hw_cfg, &feature_enabled);

	hw_cfg.num_of_mixers = sde_crtc->num_mixers;

	hw_cfg.last_feature = 0;



	for (i = 0; i < num_mixers; i++) {

		hw_dspp = sde_crtc->mixers[i].hw_dspp;

		if (!hw_dspp || i >= DSPP_MAX)

			continue;

		hw_cfg.dspp[i] = hw_dspp;

	}



	for (i = 0; i < num_mixers && !ret; i++) {

		hw_lm = sde_crtc->mixers[i].hw_lm;

		hw_dspp = sde_crtc->mixers[i].hw_dspp;

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+182 −161
Original line number Diff line number Diff line
@@ -36,48 +36,71 @@ static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp, 
	return ERR_PTR(-EINVAL);

}



static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)

static void dspp_igc(struct sde_hw_dspp *c)

{

	int i = 0, ret = 0;

	int ret = 0;



	if (!c || !c->cap || !c->cap->sblk)

		return;

	if (c->cap->sblk->igc.version == SDE_COLOR_PROCESS_VER(0x3, 0x1)) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);

		if (!ret)

			c->ops.setup_igc = reg_dmav1_setup_dspp_igcv31;

		else

			c->ops.setup_igc = sde_setup_dspp_igcv3;

	}

}



	for (i = 0; i < SDE_DSPP_MAX; i++) {

		if (!test_bit(i, &features))

			continue;

		switch (i) {

		case SDE_DSPP_PCC:

			if (c->cap->sblk->pcc.version ==

				(SDE_COLOR_PROCESS_VER(0x1, 0x7)))

static void dspp_pcc(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7)))

		c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7;

	else if (c->cap->sblk->pcc.version ==

			(SDE_COLOR_PROCESS_VER(0x4, 0x0))) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);

		if (!ret)

					c->ops.setup_pcc =

						reg_dmav1_setup_dspp_pccv4;

			c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4;

		else

					c->ops.setup_pcc =

						sde_setup_dspp_pccv4;

			}

			break;

		case SDE_DSPP_HSIC:

			if (c->cap->sblk->hsic.version ==

				SDE_COLOR_PROCESS_VER(0x1, 0x7)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

			c->ops.setup_pcc = sde_setup_dspp_pccv4;

	}

}



static void dspp_gc(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->gc.version == SDE_COLOR_PROCESS_VER(0x1, 8)) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GC, c->idx);

		if (!ret)

					c->ops.setup_pa_hsic =

						reg_dmav1_setup_dspp_pa_hsicv17;

			c->ops.setup_gc = reg_dmav1_setup_dspp_gcv18;

		/**

		 * programming for v18 through ahb is same as v17,

		 * hence assign v17 function

		 */

		else

					c->ops.setup_pa_hsic =

						sde_setup_dspp_pa_hsic_v17;

			}

			break;

		case SDE_DSPP_MEMCOLOR:

			if (c->cap->sblk->memcolor.version ==

				SDE_COLOR_PROCESS_VER(0x1, 0x7)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

			c->ops.setup_gc = sde_setup_dspp_gc_v1_7;

	}

}



static void dspp_hsic(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->hsic.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_HSIC, c->idx);

		if (!ret)

			c->ops.setup_pa_hsic = reg_dmav1_setup_dspp_pa_hsicv17;

		else

			c->ops.setup_pa_hsic = sde_setup_dspp_pa_hsic_v17;

	}

}



static void dspp_memcolor(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->memcolor.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_MEMCOLOR, c->idx);

		if (!ret) {

			c->ops.setup_pa_memcol_skin =

				reg_dmav1_setup_dspp_memcol_skinv17;
@@ -98,113 +121,110 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) 
				sde_setup_dspp_memcol_prot_v17;

		}

	}

			break;

		case SDE_DSPP_SIXZONE:

			if (c->cap->sblk->sixzone.version ==

				SDE_COLOR_PROCESS_VER(0x1, 0x7)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

				if (!ret)

					c->ops.setup_sixzone =

						reg_dmav1_setup_dspp_sixzonev17;

				else

					c->ops.setup_sixzone =

						sde_setup_dspp_sixzone_v17;

			}

			break;

		case SDE_DSPP_DITHER:

			if (c->cap->sblk->dither.version ==

				SDE_COLOR_PROCESS_VER(0x1, 0x7))

				c->ops.setup_pa_dither =

					sde_setup_dspp_dither_v1_7;

			break;

		case SDE_DSPP_VLUT:

			if (c->cap->sblk->vlut.version ==

				(SDE_COLOR_PROCESS_VER(0x1, 0x7))) {

				c->ops.setup_vlut =

				    sde_setup_dspp_pa_vlut_v1_7;

			} else if (c->cap->sblk->vlut.version ==

					(SDE_COLOR_PROCESS_VER(0x1, 0x8))) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

}



static void dspp_sixzone(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->sixzone.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SIXZONE, c->idx);

		if (!ret)

					c->ops.setup_vlut =

					reg_dmav1_setup_dspp_vlutv18;

			c->ops.setup_sixzone = reg_dmav1_setup_dspp_sixzonev17;

		else

					c->ops.setup_vlut =

					sde_setup_dspp_pa_vlut_v1_8;

			}

			break;

		case SDE_DSPP_HIST:

			if (c->cap->sblk->hist.version ==

				(SDE_COLOR_PROCESS_VER(0x1, 0x7))) {

				c->ops.setup_histogram =

				    sde_setup_dspp_hist_v1_7;

				c->ops.read_histogram =

				    sde_read_dspp_hist_v1_7;

				c->ops.lock_histogram =

				    sde_lock_dspp_hist_v1_7;

			}

			break;

		case SDE_DSPP_GAMUT:

			if (c->cap->sblk->gamut.version ==

					SDE_COLOR_PROCESS_VER(0x4, 0)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

			c->ops.setup_sixzone = sde_setup_dspp_sixzone_v17;

	}

}



static void dspp_gamut(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->gamut.version == SDE_COLOR_PROCESS_VER(0x4, 0)) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);

		if (!ret)

					c->ops.setup_gamut =

						reg_dmav1_setup_dspp_3d_gamutv4;

			c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv4;

		else

					c->ops.setup_gamut =

						sde_setup_dspp_3d_gamutv4;

			c->ops.setup_gamut = sde_setup_dspp_3d_gamutv4;

	} else if (c->cap->sblk->gamut.version ==

			SDE_COLOR_PROCESS_VER(0x4, 1)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

				if (!ret) {

					c->ops.setup_gamut =

					    reg_dmav1_setup_dspp_3d_gamutv41;

				} else {

					c->ops.setup_gamut =

					    sde_setup_dspp_3d_gamutv41;

				}

			}

			break;

		case SDE_DSPP_GC:

			if (c->cap->sblk->gc.version ==

					SDE_COLOR_PROCESS_VER(0x1, 8)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);

		if (!ret)

					c->ops.setup_gc =

						reg_dmav1_setup_dspp_gcv18;

				/** programming for v18 through ahb is same

				 * as v17 hence assign v17 function

				 */

			c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv41;

		else

					c->ops.setup_gc =

						sde_setup_dspp_gc_v1_7;

			}

			break;

		case SDE_DSPP_IGC:

			if (c->cap->sblk->igc.version ==

					SDE_COLOR_PROCESS_VER(0x3, 0x1)) {

				ret = reg_dmav1_init_dspp_op_v4(i, c->idx);

			c->ops.setup_gamut = sde_setup_dspp_3d_gamutv41;

	}

}



static void dspp_dither(struct sde_hw_dspp *c)

{

	if (c->cap->sblk->dither.version == SDE_COLOR_PROCESS_VER(0x1, 0x7))

		c->ops.setup_pa_dither = sde_setup_dspp_dither_v1_7;

}



static void dspp_hist(struct sde_hw_dspp *c)

{

	if (c->cap->sblk->hist.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {

		c->ops.setup_histogram = sde_setup_dspp_hist_v1_7;

		c->ops.read_histogram = sde_read_dspp_hist_v1_7;

		c->ops.lock_histogram = sde_lock_dspp_hist_v1_7;

	}

}



static void dspp_vlut(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->vlut.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {

		c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_7;

	} else if (c->cap->sblk->vlut.version ==

			(SDE_COLOR_PROCESS_VER(0x1, 0x8))) {

		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_VLUT, c->idx);

		if (!ret)

					c->ops.setup_igc =

						reg_dmav1_setup_dspp_igcv31;

			c->ops.setup_vlut = reg_dmav1_setup_dspp_vlutv18;

		else

					c->ops.setup_igc =

						sde_setup_dspp_igcv3;

			c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_8;

	}

			break;

		case SDE_DSPP_AD:

			if (c->cap->sblk->ad.version ==

			    SDE_COLOR_PROCESS_VER(4, 0)) {

}



static void dspp_ad(struct sde_hw_dspp *c)

{

	if (c->cap->sblk->ad.version == SDE_COLOR_PROCESS_VER(4, 0)) {

		c->ops.setup_ad = sde_setup_dspp_ad4;

				c->ops.ad_read_intr_resp =

					sde_read_intr_resp_ad4;

		c->ops.ad_read_intr_resp = sde_read_intr_resp_ad4;

		c->ops.validate_ad = sde_validate_dspp_ad4;

	}

			break;

		default:

			break;

}



static void (*dspp_blocks[SDE_DSPP_MAX])(struct sde_hw_dspp *c);



static void _init_dspp_ops(void)

{

	dspp_blocks[SDE_DSPP_IGC] = dspp_igc;

	dspp_blocks[SDE_DSPP_PCC] = dspp_pcc;

	dspp_blocks[SDE_DSPP_GC] = dspp_gc;

	dspp_blocks[SDE_DSPP_HSIC] = dspp_hsic;

	dspp_blocks[SDE_DSPP_MEMCOLOR] = dspp_memcolor;

	dspp_blocks[SDE_DSPP_SIXZONE] = dspp_sixzone;

	dspp_blocks[SDE_DSPP_GAMUT] = dspp_gamut;

	dspp_blocks[SDE_DSPP_DITHER] = dspp_dither;

	dspp_blocks[SDE_DSPP_HIST] = dspp_hist;

	dspp_blocks[SDE_DSPP_VLUT] = dspp_vlut;

	dspp_blocks[SDE_DSPP_AD] = dspp_ad;

}



static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)

{

	int i = 0;



	if (!c->cap->sblk)

		return;



	for (i = 0; i < SDE_DSPP_MAX; i++) {

		if (!test_bit(i, &features))

			continue;

		if (dspp_blocks[i])

			dspp_blocks[i](c);

	}

}
@@ -244,6 +264,7 @@ struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx, 
	/* Assign ops */

	c->idx = idx;

	c->cap = cfg;

	_init_dspp_ops();

	_setup_dspp_ops(c, c->cap->features);



	rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_DSPP, idx, &sde_hw_ops);

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+2 −0
Original line number Diff line number Diff line
@@ -518,6 +518,7 @@ struct sde_mdss_color { 
 * @mixer_info: mixer info pointer associated with lm.

 * @displayv: height of the display.

 * @displayh: width of the display.

 * @dspp[DSPP_MAX]: array of hw_dspp pointers associated with crtc.

 */

struct sde_hw_cp_cfg {

	void *payload;
@@ -528,6 +529,7 @@ struct sde_hw_cp_cfg { 
	void *mixer_info;

	u32 displayv;

	u32 displayh;

	struct sde_hw_dspp *dspp[DSPP_MAX];

};



/**