Commit 24bf7ae3 authored Jan 19, 2017 by Ilia Mirkin Committed by Ben Skeggs Jan 31, 2017

drm/nouveau/nv1a,nv1f/disp: fix memory clock rate retrieval

Based on the xf86-video-nv code, NFORCE (NV1A) and NFORCE2 (NV1F) have a
different way of retrieving clocks. See the
nv_hw.c:nForceUpdateArbitrationSettings function in the original code
for how these clocks were accessed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54587


Cc: stable@vger.kernel.org
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

parent d347583a

drivers/gpu/drm/nouveau/dispnv04/hw.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -222,6 +222,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
		uint32_t mpllP;

		pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
		mpllP = (mpllP >> 8) & 0xf;
		if (!mpllP)
		mpllP = 4;

		@@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
		uint32_t clock;

		pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
		return clock;
		return clock / 1000;
		}

		ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);