Loading drivers/bus/mhi/core/mhi_pm.c +5 −0 Original line number Diff line number Diff line Loading @@ -1145,6 +1145,11 @@ int mhi_pm_fast_suspend(struct mhi_controller *mhi_cntrl, bool notify_client) return -EBUSY; } /* wait here if controller wants device to be in M2 before proceeding */ wait_event_timeout(mhi_cntrl->state_event, mhi_cntrl->dev_state == MHI_STATE_M2, msecs_to_jiffies(mhi_cntrl->m2_timeout_ms)); /* disable ctrl event processing */ tasklet_disable(&mhi_cntrl->mhi_event->task); Loading drivers/net/wireless/cnss2/debug.c +4 −0 Original line number Diff line number Diff line Loading @@ -557,6 +557,8 @@ static ssize_t cnss_control_params_debug_write(struct file *fp, plat_priv->ctrl_params.quirks = val; else if (strcmp(cmd, "mhi_timeout") == 0) plat_priv->ctrl_params.mhi_timeout = val; else if (strcmp(cmd, "mhi_m2_timeout") == 0) plat_priv->ctrl_params.mhi_m2_timeout = val; else if (strcmp(cmd, "qmi_timeout") == 0) plat_priv->ctrl_params.qmi_timeout = val; else if (strcmp(cmd, "bdf_type") == 0) Loading Loading @@ -641,6 +643,8 @@ static int cnss_control_params_debug_show(struct seq_file *s, void *data) seq_puts(s, "\nCurrent value:\n"); cnss_show_quirks_state(s, cnss_priv); seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout); seq_printf(s, "mhi_m2_timeout: %u\n", cnss_priv->ctrl_params.mhi_m2_timeout); seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout); seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type); seq_printf(s, "time_sync_period: %u\n", Loading drivers/net/wireless/cnss2/main.c +2 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ #else #define CNSS_MHI_TIMEOUT_DEFAULT 0 #endif #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25 #define CNSS_QMI_TIMEOUT_DEFAULT 10000 #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000 Loading Loading @@ -1931,6 +1932,7 @@ static void cnss_init_control_params(struct cnss_plat_data *plat_priv) { plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT; plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT; plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT; plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT; plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT; plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT; Loading drivers/net/wireless/cnss2/main.h +1 −0 Original line number Diff line number Diff line Loading @@ -261,6 +261,7 @@ struct cnss_cal_info { struct cnss_control_params { unsigned long quirks; unsigned int mhi_timeout; unsigned int mhi_m2_timeout; unsigned int qmi_timeout; unsigned int bdf_type; unsigned int time_sync_period; Loading drivers/net/wireless/cnss2/pci.c +2 −0 Original line number Diff line number Diff line Loading @@ -57,6 +57,7 @@ static DEFINE_SPINLOCK(pci_link_down_lock); static DEFINE_SPINLOCK(pci_reg_window_lock); #define MHI_TIMEOUT_OVERWRITE_MS (plat_priv->ctrl_params.mhi_timeout) #define MHI_M2_TIMEOUT_MS (plat_priv->ctrl_params.mhi_m2_timeout) #define FORCE_WAKE_DELAY_MIN_US 4000 #define FORCE_WAKE_DELAY_MAX_US 6000 Loading Loading @@ -937,6 +938,7 @@ int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv) if (MHI_TIMEOUT_OVERWRITE_MS) pci_priv->mhi_ctrl->timeout_ms = MHI_TIMEOUT_OVERWRITE_MS; pci_priv->mhi_ctrl->m2_timeout_ms = MHI_M2_TIMEOUT_MS; ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_INIT); if (ret) Loading Loading
drivers/bus/mhi/core/mhi_pm.c +5 −0 Original line number Diff line number Diff line Loading @@ -1145,6 +1145,11 @@ int mhi_pm_fast_suspend(struct mhi_controller *mhi_cntrl, bool notify_client) return -EBUSY; } /* wait here if controller wants device to be in M2 before proceeding */ wait_event_timeout(mhi_cntrl->state_event, mhi_cntrl->dev_state == MHI_STATE_M2, msecs_to_jiffies(mhi_cntrl->m2_timeout_ms)); /* disable ctrl event processing */ tasklet_disable(&mhi_cntrl->mhi_event->task); Loading
drivers/net/wireless/cnss2/debug.c +4 −0 Original line number Diff line number Diff line Loading @@ -557,6 +557,8 @@ static ssize_t cnss_control_params_debug_write(struct file *fp, plat_priv->ctrl_params.quirks = val; else if (strcmp(cmd, "mhi_timeout") == 0) plat_priv->ctrl_params.mhi_timeout = val; else if (strcmp(cmd, "mhi_m2_timeout") == 0) plat_priv->ctrl_params.mhi_m2_timeout = val; else if (strcmp(cmd, "qmi_timeout") == 0) plat_priv->ctrl_params.qmi_timeout = val; else if (strcmp(cmd, "bdf_type") == 0) Loading Loading @@ -641,6 +643,8 @@ static int cnss_control_params_debug_show(struct seq_file *s, void *data) seq_puts(s, "\nCurrent value:\n"); cnss_show_quirks_state(s, cnss_priv); seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout); seq_printf(s, "mhi_m2_timeout: %u\n", cnss_priv->ctrl_params.mhi_m2_timeout); seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout); seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type); seq_printf(s, "time_sync_period: %u\n", Loading
drivers/net/wireless/cnss2/main.c +2 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ #else #define CNSS_MHI_TIMEOUT_DEFAULT 0 #endif #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25 #define CNSS_QMI_TIMEOUT_DEFAULT 10000 #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000 Loading Loading @@ -1931,6 +1932,7 @@ static void cnss_init_control_params(struct cnss_plat_data *plat_priv) { plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT; plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT; plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT; plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT; plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT; plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT; Loading
drivers/net/wireless/cnss2/main.h +1 −0 Original line number Diff line number Diff line Loading @@ -261,6 +261,7 @@ struct cnss_cal_info { struct cnss_control_params { unsigned long quirks; unsigned int mhi_timeout; unsigned int mhi_m2_timeout; unsigned int qmi_timeout; unsigned int bdf_type; unsigned int time_sync_period; Loading
drivers/net/wireless/cnss2/pci.c +2 −0 Original line number Diff line number Diff line Loading @@ -57,6 +57,7 @@ static DEFINE_SPINLOCK(pci_link_down_lock); static DEFINE_SPINLOCK(pci_reg_window_lock); #define MHI_TIMEOUT_OVERWRITE_MS (plat_priv->ctrl_params.mhi_timeout) #define MHI_M2_TIMEOUT_MS (plat_priv->ctrl_params.mhi_m2_timeout) #define FORCE_WAKE_DELAY_MIN_US 4000 #define FORCE_WAKE_DELAY_MAX_US 6000 Loading Loading @@ -937,6 +938,7 @@ int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv) if (MHI_TIMEOUT_OVERWRITE_MS) pci_priv->mhi_ctrl->timeout_ms = MHI_TIMEOUT_OVERWRITE_MS; pci_priv->mhi_ctrl->m2_timeout_ms = MHI_M2_TIMEOUT_MS; ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_INIT); if (ret) Loading