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Commit 2440d29d authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: dts: realview: support all the RealView EB board variants 



The ARM RealView Evaluation Baseboards are basically these:

- The original ARMv5 EB board with an ARM926EJ-S, ARM1136 or
  ARM1176 core tile here described in arm-realview-eb.dts
  no matter which of these core tiles is being used. This
  can be emulated by QEMU "realview-eb" machine, which by
  default will have the ARM926EJ-S core tile.

- The same board with one of three MPCore Core tiles:
  ARM11MPCore, not to be confused with the similar ARM
  PB11MPCore ARM11MPCore test system. This exist in
  two revisions:
  - Revision A modeled in arm-realview-eb-11mp.dts
  - Revision B modeled arm-realview-eb-11mp-revb.dts
    Revision B can be emulated by the QEMU
    "realview-eb-mpcore" machine, but to match the hardware
    also the argument -smp cpus=4 must be passed so that
    it has four CPU cores, like the hardware.

  There is also evidently from the code in the kernel a
  Cortex-A9 core tile for the EB, and this is modeled in
  arm-realview-eb-a9mp.dts based on the kernel boardfile.
  I have not found a user guide for this EB core tile on
  the ARM website and it seems uncommon. It is however
  included for completeness.

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 95109b8b

arch/arm/boot/dts/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -552,7 +552,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \ 
	qcom-msm8974-sony-xperia-honami.dtb

dtb-$(CONFIG_ARCH_REALVIEW) += \

	arm-realview-pb1176.dtb \

	arm-realview-pb11mp.dtb

	arm-realview-pb11mp.dtb \

	arm-realview-eb.dtb \

	arm-realview-eb-11mp.dtb \

	arm-realview-eb-11mp-revb.dtb \

	arm-realview-eb-a9mp.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += \

	rk3036-evb.dtb \

	rk3036-kylin.dtb \

arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts

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+93 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Linaro Ltd

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "arm-realview-eb-11mp.dts"



/ {

	model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B";

};



/*

 * The revision B has a distinctly different layout of the syscon, so

 * append a specific compatible-string.

 */

&syscon {

	compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd";

};



&intc {

	reg = <0x10101000 0x1000>,

	      <0x10100100 0x100>;

};



&L2 {

	reg = <0x10102000 0x1000>;

};



&scu {

	reg = <0x10100000 0x100>;

};



&twd_timer {

	reg = <0x10100600 0x20>;

};



&twd_wdog {

	reg = <0x10100620 0x20>;

};



/*

 * On revision B, we cannot reach the secondary interrupt

 * controller, as a result, some peripherals that are dependent

 * on their IRQ cannot be reached, so disable them.

 */

&intc_second {

	status = "disabled";

};



&gpio0 {

	status = "disabled";

};



&gpio1 {

	status = "disabled";

};



&gpio2 {

	status = "disabled";

};



&serial2 {

	status = "disabled";

};



&serial3 {

	status = "disabled";

};



&ssp {

	status = "disabled";

};



&wdog {

	status = "disabled";

};

arch/arm/boot/dts/arm-realview-eb-11mp.dts

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+74 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Linaro Ltd

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



/dts-v1/;

#include "arm-realview-eb-mp.dtsi"



/ {

	model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C";

	arm,hbi = <0x146>;



	/*

	 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.

	 * Reference: ARM DUI 0318F

	 *

	 * To run this machine with QEMU, specify the following:

	 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4

	 */

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "arm,realview-smp";



		MP11_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,arm11mpcore";

			reg = <0>;

			next-level-cache = <&L2>;

		};



		MP11_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,arm11mpcore";

			reg = <1>;

			next-level-cache = <&L2>;

		};



		MP11_2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,arm11mpcore";

			reg = <2>;

			next-level-cache = <&L2>;

		};



		MP11_3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,arm11mpcore";

			reg = <3>;

			next-level-cache = <&L2>;

		};

	};

};



&pmu {

	interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;

};

arch/arm/boot/dts/arm-realview-eb-a9mp.dts

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+70 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Linaro Ltd

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



/dts-v1/;

#include "arm-realview-eb-mp.dtsi"



/ {

	model = "ARM RealView EB Cortex A9 MPCore";



	/*

	 * This is the Cortex A9 MPCore tile used with the

	 * RealView EB.

	 */

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "arm,realview-smp";



		A9_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			next-level-cache = <&L2>;

		};



		A9_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			next-level-cache = <&L2>;

		};



		A9_2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <2>;

			next-level-cache = <&L2>;

		};



		A9_3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <3>;

			next-level-cache = <&L2>;

		};

	};

};



&pmu {

	interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;

};

arch/arm/boot/dts/arm-realview-eb-mp.dtsi

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+225 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Linaro Ltd

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/gpio/gpio.h>

#include "arm-realview-eb.dtsi"



/*

 * This is the common include file for all MPCore variants of the

 * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B

 * and Cortex-A9 MPCore.

 */

/ {

	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "arm,realview-eb-soc", "simple-bus";

		regmap = <&syscon>;

		ranges;



		/* Primary interrupt controller in the test chip */

		intc: interrupt-controller@1f000100 {

			compatible = "arm,eb11mp-gic";

			#interrupt-cells = <3>;

			#address-cells = <1>;

			interrupt-controller;

			reg = <0x1f001000 0x1000>,

			      <0x1f000100 0x100>;

		};



		/* Secondary interrupt controller on the FPGA */

		intc_second: interrupt-controller@10040000 {

			compatible = "arm,pl390";

			#interrupt-cells = <3>;

			#address-cells = <1>;

			interrupt-controller;

			reg = <0x10041000 0x1000>,

			      <0x10040000 0x100>;

			interrupt-parent = <&intc>;

			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;

		};



		L2: l2-cache {

			compatible = "arm,l220-cache";

			reg = <0x1f002000 0x1000>;

			interrupt-parent = <&intc>;

			interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,

			     <0 30 IRQ_TYPE_LEVEL_HIGH>,

			     <0 31 IRQ_TYPE_LEVEL_HIGH>;

			cache-unified;

			cache-level = <2>;

			/*

			 * Override default cache size, sets and

			 * associativity as these may be erroneously set

			 * up by boot loader(s), probably for safety

			 * since th outer sync operation can cause the

			 * cache to hang unless disabled.

			 */

			cache-size = <1048576>; // 1MB

			cache-sets = <4096>;

			cache-line-size = <32>;

			arm,shared-override;

			arm,parity-enable;

			arm,outer-sync-disable;

		};



		scu: scu@1f000000 {

			compatible = "arm,arm11mp-scu";

			reg = <0x1f000000 0x100>;

		};



		twd_timer: timer@1f000600 {

			compatible = "arm,arm11mp-twd-timer";

			reg = <0x1f000600 0x20>;

			interrupt-parent = <&intc>;

			interrupts = <1 13 0xf04>;

		};



		twd_wdog: watchdog@1f000620 {

			compatible = "arm,arm11mp-twd-wdt";

			reg = <0x1f000620 0x20>;

			interrupt-parent = <&intc>;

			interrupts = <1 14 0xf04>;

		};



		/* PMU with one IRQ line per core */

		pmu: pmu@0 {

			compatible = "arm,arm11mpcore-pmu";

			interrupt-parent = <&intc>;

			interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,

			     <0 18 IRQ_TYPE_LEVEL_HIGH>,

			     <0 19 IRQ_TYPE_LEVEL_HIGH>,

			     <0 20 IRQ_TYPE_LEVEL_HIGH>;

		};

	};

};



/*

 * This adapts all the peripherals to the interrupt routing

 * to the GIC on the core tile.

 */



&ethernet {

	interrupt-parent = <&intc>;

	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;

};



&usb {

	interrupt-parent = <&intc>;

	interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;

};



&aaci {

	interrupt-parent = <&intc>;

	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;

};



&mmc {

	interrupt-parent = <&intc>;

	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,

			<0 15 IRQ_TYPE_LEVEL_HIGH>;

};



&kmi0 {

	interrupt-parent = <&intc>;

	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;

};



&kmi1 {

	interrupt-parent = <&intc>;

	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;

};



&charlcd {

	interrupt-parent = <&intc>;

	interrupts = <0  IRQ_TYPE_LEVEL_HIGH>;

};



&serial0 {

	interrupt-parent = <&intc>;

	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;

};



&serial1 {

	interrupt-parent = <&intc>;

	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;

};



&timer01 {

	interrupt-parent = <&intc>;

	interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;

};



&timer23 {

	interrupt-parent = <&intc>;

	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;

};



&rtc {

	interrupt-parent = <&intc>;

	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;

};



/*

 * On revision A, these peripherals does not have their IRQ lines

 * routed to the core tile, but they can be reached on the secondary

 * GIC.

 */

&gpio0 {

	interrupt-parent = <&intc_second>;

	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;

};



&gpio1 {

	interrupt-parent = <&intc_second>;

	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;

};



&gpio2 {

	interrupt-parent = <&intc_second>;

	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;

};



&serial2 {

	interrupt-parent = <&intc_second>;

	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;

	status = "okay";

};



&serial3 {

	interrupt-parent = <&intc_second>;

	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;

	status = "okay";

};



&ssp {

	interrupt-parent = <&intc_second>;

	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;

	status = "okay";

};



&wdog {

	interrupt-parent = <&intc_second>;

	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;

	status = "okay";

};